ahbl read write fsm missing default and runs 1 timer more than intended

[M0stafaRady]

The following FSM misses a default condition and it read and write 1 time after the done signal asserted.

MS_DMAC_AHBL/hdl/rtl/MS_DMAC_AHBL.v

Lines 121 to 137 in d638184

	always @*
	case(state)
	IDLE_STATE: if(TRIG_REG & CTRL_REG_EN)
	nstate = RA_STATE;
	else
	nstate = IDLE_STATE;
	RA_STATE: if(M_HREADY) nstate = RD_STATE; else nstate = RA_STATE;
	RD_STATE: if(M_HREADY) nstate = WA_STATE; else nstate = RD_STATE;
	WA_STATE: if(M_HREADY) nstate = WD_STATE; else nstate = WA_STATE;
	WD_STATE: if(M_HREADY) begin
	if(done)
	nstate = IDLE_STATE;
	else
	nstate = RA_STATE;
	end else nstate = WA_STATE;
	endcase