Ninth lab assignment for CSE2441 (Introduction to Digital Logic). Implementing the TRISC Processor Control Unit.
The TRISC organization is
The TRISC Instruction Set for Lab 9 is
And the Controller Finite State Machine (FSM) State Diagram for INC and CLR Instructions is
The lab was done in multiple parts:
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The first part was to build an Instruction Decoder (ID) that can receive the input and decode it.
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The second part was to build a Three Instruction Controller - which is a Controller that can execute three instructions -> INC, CLR, and JMP (Increment, Clear, and Jump commands).
NOTE: The Three Instruction Controller has two files - one where I wrote the verilog code, and created a symbol file. The second is where I used the symbol file to create a .bdf (block diagram file) using the mentioned symbol file
The bdf of our Three Instruction Controller is
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The third part was to build a Six Instruction Controller - which is a Controller that can execute six instructions -> INC, CLR, JMP, LDA, STA, and ADD (Increment ACC, Clear ACC, Jump, Load ACC, Store ACC, and Add ACC instructions).
NOTE: The Six Instruction Controller has two files - one where I wrote the verilog code, and created a symbol file. The second is where I used the symbol file to create a .bdf (block diagram file) using the mentioned symbol file -
And the final part was a bonus question where we combined the Instruction Decoder and Six Instruction Controller and demonstrated it on the DE1 Altera Board to the teacher.
The bdf of our Six Instruction Controller is
