All notable changes to this project will be documented in this file.
The format is based on Keep a Changelog and this project adheres to Semantic Versioning.
- Instruction cache added
- Support for Verilator
- CI support for verilator
- Update documentation
- Non-blocking data cache
- Two AXI interfaces on top level, one for bypassing and one for actual cache-able regions
- Performance Counters
- Hardware multiplication (full M-Extension)
- Support for inter processor interrupts (IPI)
- Testbench: EOC component now listening on store interface only
- Store interfaces has been simplified by removing the
validsignal, a transaction is now considered finished as soon as the dcache gives the grant signal. - EOC and dcache checker has been reworked to get rid of absolute path in UVM testbench
- Fix problem when bypassing the data cache
Linux booting on FPGA.
- Support for M Extension (mul, div and reminder) in simulation
- Preliminary debug support
- Added support for cache management instructions
- Various bug fixes (branch-prediction, PTW and TLB problems, interrupt handling)
- Fixed synthesis issues
0.3.0 - 2017-07-15
- Added support for device tree in Ariane's testbench
- Bugfixes in compressed decoder (legal shifts where throwing an illegal instruction although they where legal)
- Increase memory size to 16 MB in-order to simulate a full Linux boot
- Re-worked timer facilities in the CSR section, moved to a platform RTC
- Core completed its first full Linux boot
- Changelog design, adhering to a common standard
0.2.0 - 2017-06-28
- Virtual memory support according to RISC-V privilege specification 1.11 (WIP)
- Add support for Torture test framework
- IPC improvements
- Timing improvements
- New fetch interface, smaller and ready for macro-op fusion and dual-issue
0.1.0 - 2017-06-21
- Initial development, getting to a stable point