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The instructions SLLV, SLL, and EQ` are usable with two different opcodes, as shown in Table 6 of the documentation. The duplicate opcodes, which the assembler does not use, should raise an "invalid instruction" trap instead.
The text was updated successfully, but these errors were encountered:
The instructions
SLLV,
SLL, and
EQ` are usable with two different opcodes, as shown in Table 6 of the documentation. The duplicate opcodes, which the assembler does not use, should raise an "invalid instruction" trap instead.The text was updated successfully, but these errors were encountered: