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cv32e40s_rvfi.sv
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cv32e40s_rvfi.sv
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// Copyright (c) 2020 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// CV32E40S RVFI interface
// Contributors: Davide Schiavone <davide@openhwgroup.org>
// Halfdan Bechmann <halfdan.bechmann@silabs.com>
module cv32e40s_rvfi
import cv32e40s_pkg::*;
import cv32e40s_rvfi_pkg::*;
#(
parameter bit CLIC = 0,
parameter bit DEBUG = 1
)
(
input logic clk_i,
input logic rst_ni,
// Non-pipeline Probes
cv32e40s_if_c_obi.monitor m_c_obi_instr_if,
//// IF Probes ////
input logic if_valid_i,
input logic [31:0] pc_if_i,
input logic instr_pmp_err_if_i,
input logic last_op_if_i,
input logic abort_op_if_i,
input logic prefetch_valid_if_i,
input logic prefetch_ready_if_i,
input logic [31:0] prefetch_addr_if_i,
input logic prefetch_compressed_if_i,
input inst_resp_t prefetch_instr_if_i,
input logic clic_ptr_if_i,
input logic mret_ptr_if_i,
input mpu_status_e mpu_status_i,
input logic prefetch_trans_valid_i,
input logic prefetch_trans_ready_i,
input logic prefetch_resp_valid_i,
// ID probes
input logic id_valid_i,
input logic id_ready_i,
input logic [31:0] pc_id_i,
input logic [ 1:0] rf_re_id_i,
input logic sys_mret_id_i,
input logic tbljmp_id_i,
input logic jump_in_id_i,
input logic is_compressed_id_i,
input logic lsu_en_id_i,
input logic lsu_we_id_i,
input logic [1:0] lsu_size_id_i,
input logic [4:0] rs1_addr_id_i,
input logic [4:0] rs2_addr_id_i,
input logic [31:0] operand_a_fw_id_i,
input logic [31:0] operand_b_fw_id_i,
input logic first_op_id_i,
input logic hint_id_i,
input logic clic_ptr_in_id_i,
input logic mret_ptr_in_id_i,
// EX probes
input logic ex_ready_i,
input logic ex_valid_i,
input logic branch_in_ex_i,
input logic branch_decision_ex_i,
input logic dret_in_ex_i,
input logic lsu_en_ex_i,
input logic lsu_pmp_err_ex_i,
input logic lsu_pma_err_ex_i,
input logic lsu_pma_err_atomic_ex_i,
input pma_cfg_t lsu_pma_cfg_ex_i,
input logic lsu_misaligned_ex_i,
input obi_data_req_t buffer_trans_ex_i,
input logic buffer_trans_valid_ex_i,
input logic lsu_split_q_ex_i,
input logic lsu_split_0_ex_i,
// WB probes
input logic wb_ready_i,
input logic wb_valid_i,
input logic [31:0] pc_wb_i,
input logic [31:0] instr_rdata_wb_i,
input logic is_dummy_instr_wb_i,
input logic ebreak_in_wb_i,
input logic csr_en_wb_i,
input logic sys_wfi_insn_wb_i,
input logic sys_en_wb_i,
input logic last_op_wb_i,
input logic first_op_wb_i,
input logic abort_op_wb_i,
input logic rf_we_wb_i,
input logic [4:0] rf_addr_wb_i,
input logic [31:0] rf_wdata_wb_i,
input logic [31:0] lsu_rdata_wb_i,
input logic mret_ptr_wb_i,
input logic clic_ptr_wb_i,
input logic hint_wb_i,
input logic csr_mscratchcsw_in_wb_i,
input logic csr_mscratchcswl_in_wb_i,
input logic csr_mnxti_in_wb_i,
input logic [31:0] wpt_match_wb_i,
input mpu_status_e mpu_status_wb_i,
// PC
input logic [31:0] branch_addr_n_i,
input privlvl_t priv_lvl_i,
// Controller FSM probes
input ctrl_fsm_t ctrl_fsm_i,
input ctrl_state_e ctrl_fsm_cs_i,
input ctrl_state_e ctrl_fsm_ns_i,
input logic pending_single_step_i,
input logic single_step_allowed_i,
input logic nmi_pending_i, // regular NMI pending
input logic nmi_is_store_i, // regular NMI type
input logic debug_mode_q_i,
input logic [2:0] debug_cause_n_i,
input logic etrigger_in_wb_i,
// Interrupt Controller probes
input logic [31:0] irq_i,
input logic irq_wu_ctrl_i,
input logic [9:0] irq_id_ctrl_i,
//// CSR Probes ////
input jvt_t csr_jvt_n_i,
input jvt_t csr_jvt_q_i,
input logic csr_jvt_we_i,
input mstatus_t csr_mstatus_n_i,
input mstatus_t csr_mstatus_q_i,
input logic csr_mstatus_we_i,
input mstatush_t csr_mstatush_n_i,
input mstatush_t csr_mstatush_q_i,
input logic csr_mstatush_we_i,
input logic [31:0] csr_misa_n_i,
input logic [31:0] csr_misa_q_i,
input logic csr_misa_we_i,
input logic [31:0] csr_mie_n_i,
input logic [31:0] csr_mie_q_i,
input logic csr_mie_we_i,
input mtvec_t csr_mtvec_n_i,
input mtvec_t csr_mtvec_q_i,
input logic csr_mtvec_we_i,
input mtvt_t csr_mtvt_n_i,
input mtvt_t csr_mtvt_q_i,
input logic csr_mtvt_we_i,
input logic [31:0] csr_mcountinhibit_n_i,
input logic [31:0] csr_mcountinhibit_q_i,
input logic csr_mcountinhibit_we_i,
input logic [31:0] [31:0] csr_mhpmevent_n_i,
input logic [31:0] [31:0] csr_mhpmevent_q_i,
input logic [31:0] csr_mhpmevent_we_i,
input logic [31:0] csr_mscratch_n_i,
input logic [31:0] csr_mscratch_q_i,
input logic csr_mscratch_we_i,
input logic [31:0] csr_mepc_n_i,
input logic [31:0] csr_mepc_q_i,
input logic csr_mepc_we_i,
input mcause_t csr_mcause_n_i,
input mcause_t csr_mcause_q_i,
input logic csr_mcause_we_i,
input logic [31:0] csr_mip_n_i,
input logic [31:0] csr_mip_q_i,
input logic csr_mip_we_i,
input logic [31:0] csr_mnxti_n_i,
input logic [31:0] csr_mnxti_q_i,
input logic csr_mnxti_we_i,
input mintstatus_t csr_mintstatus_n_i,
input mintstatus_t csr_mintstatus_q_i,
input logic csr_mintstatus_we_i,
input logic [31:0] csr_mintthresh_n_i,
input logic [31:0] csr_mintthresh_q_i,
input logic csr_mintthresh_we_i,
input logic [31:0] csr_mscratchcsw_n_i,
input logic [31:0] csr_mscratchcsw_q_i,
input logic csr_mscratchcsw_we_i,
input logic [31:0] csr_mscratchcswl_n_i,
input logic [31:0] csr_mscratchcswl_q_i,
input logic csr_mscratchcswl_we_i,
input logic [31:0] csr_tdata1_n_i,
input logic [31:0] csr_tdata1_q_i,
input logic csr_tdata1_we_i,
input logic [31:0] csr_tdata2_n_i,
input logic [31:0] csr_tdata2_q_i,
input logic csr_tdata2_we_i,
input logic [31:0] csr_tinfo_n_i,
input logic [31:0] csr_tinfo_q_i,
input logic csr_tinfo_we_i,
input logic [31:0] csr_tselect_n_i,
input logic [31:0] csr_tselect_q_i,
input logic csr_tselect_we_i,
input dcsr_t csr_dcsr_n_i,
input dcsr_t csr_dcsr_q_i,
input logic csr_dcsr_we_i,
input logic [31:0] csr_dpc_n_i,
input logic [31:0] csr_dpc_q_i,
input logic csr_dpc_we_i,
input logic [31:0] csr_dscratch0_n_i,
input logic [31:0] csr_dscratch0_q_i,
input logic csr_dscratch0_we_i,
input logic [31:0] csr_dscratch1_n_i,
input logic [31:0] csr_dscratch1_q_i,
input logic csr_dscratch1_we_i,
input logic [31:0] csr_mconfigptr_n_i,
input logic [31:0] csr_mconfigptr_q_i,
input logic csr_mconfigptr_we_i,
// performance counters
// cycle, instret, hpcounter, cycleh, instreth, hpcounterh
// mcycle, minstret, mhpcounter, mcycleh, minstreth, mhpcounterh
input logic [31:0] [63:0] csr_mhpmcounter_n_i,
input logic [31:0] [63:0] csr_mhpmcounter_q_i,
input logic [31:0] [1:0] csr_mhpmcounter_we_i,
input logic [31:0] csr_mvendorid_i,
input logic [31:0] csr_marchid_i,
input logic [31:0] csr_mhartid_i,
input logic [31:0] csr_mimpid_i,
input logic [31:0] csr_mcounteren_n_i,
input logic [31:0] csr_mcounteren_q_i,
input logic csr_mcounteren_we_i,
input logic [ 7:0] csr_pmpncfg_n_i[PMP_MAX_REGIONS],
input logic [ 7:0] csr_pmpncfg_q_i[PMP_MAX_REGIONS],
input logic [PMP_MAX_REGIONS-1:0] csr_pmpncfg_we_i,
input logic [31:0] csr_pmpaddr_n_i[PMP_MAX_REGIONS],
input logic [31:0] csr_pmpaddr_q_i[PMP_MAX_REGIONS],
input logic [PMP_MAX_REGIONS-1:0] csr_pmpaddr_we_i,
input logic [31:0] csr_mseccfg_n_i,
input logic [31:0] csr_mseccfg_q_i,
input logic csr_mseccfg_we_i,
input logic [31:0] csr_mseccfgh_n_i,
input logic [31:0] csr_mseccfgh_q_i,
input logic csr_mseccfgh_we_i,
input logic [31:0] csr_menvcfg_n_i,
input logic [31:0] csr_menvcfg_q_i,
input logic csr_menvcfg_we_i,
input logic [31:0] csr_menvcfgh_n_i,
input logic [31:0] csr_menvcfgh_q_i,
input logic csr_menvcfgh_we_i,
input logic [31:0] csr_cpuctrl_n_i,
input logic [31:0] csr_cpuctrl_q_i,
input logic csr_cpuctrl_we_i,
input logic [31:0] csr_secureseed0_n_i,
input logic [31:0] csr_secureseed0_q_i,
input logic csr_secureseed0_we_i,
input logic [31:0] csr_secureseed1_n_i,
input logic [31:0] csr_secureseed1_q_i,
input logic csr_secureseed1_we_i,
input logic [31:0] csr_secureseed2_n_i,
input logic [31:0] csr_secureseed2_q_i,
input logic csr_secureseed2_we_i,
input logic [31:0] csr_mstateen0_n_i,
input logic [31:0] csr_mstateen0_q_i,
input logic csr_mstateen0_we_i,
input logic [31:0] csr_mstateen1_n_i,
input logic [31:0] csr_mstateen1_q_i,
input logic csr_mstateen1_we_i,
input logic [31:0] csr_mstateen2_n_i,
input logic [31:0] csr_mstateen2_q_i,
input logic csr_mstateen2_we_i,
input logic [31:0] csr_mstateen3_n_i,
input logic [31:0] csr_mstateen3_q_i,
input logic csr_mstateen3_we_i,
input logic [31:0] csr_mstateen0h_n_i,
input logic [31:0] csr_mstateen0h_q_i,
input logic csr_mstateen0h_we_i,
input logic [31:0] csr_mstateen1h_n_i,
input logic [31:0] csr_mstateen1h_q_i,
input logic csr_mstateen1h_we_i,
input logic [31:0] csr_mstateen2h_n_i,
input logic [31:0] csr_mstateen2h_q_i,
input logic csr_mstateen2h_we_i,
input logic [31:0] csr_mstateen3h_n_i,
input logic [31:0] csr_mstateen3h_q_i,
input logic csr_mstateen3h_we_i,
// RISC-V Formal Interface
// Does not comply with the coding standards of _i/_o suffixes, but follow,
// the convention of RISC-V Formal Interface Specification.
output logic [ 0:0] rvfi_valid,
output logic [63:0] rvfi_order,
output logic [31:0] rvfi_insn,
output logic [2:0] rvfi_instr_prot,
output logic [1:0] rvfi_instr_memtype,
output logic rvfi_instr_dbg,
output rvfi_trap_t rvfi_trap,
output logic [ 0:0] rvfi_halt,
output rvfi_intr_t rvfi_intr,
output logic [ 1:0] rvfi_mode,
output logic [ 1:0] rvfi_ixl,
output logic [ 1:0] rvfi_nmip,
output logic [ 2:0] rvfi_dbg,
output logic [ 0:0] rvfi_dbg_mode,
output logic [ 4:0] rvfi_rd_addr,
output logic [31:0] rvfi_rd_wdata,
output logic [ 4:0] rvfi_rs1_addr,
output logic [ 4:0] rvfi_rs2_addr,
output logic [31:0] rvfi_rs1_rdata,
output logic [31:0] rvfi_rs2_rdata,
output logic [31:0] rvfi_pc_rdata,
output logic [31:0] rvfi_pc_wdata,
output logic [32*NMEM-1:0] rvfi_mem_addr,
output logic [ 4*NMEM-1:0] rvfi_mem_rmask,
output logic [ 4*NMEM-1:0] rvfi_mem_wmask,
output logic [32*NMEM-1:0] rvfi_mem_rdata,
output logic [32*NMEM-1:0] rvfi_mem_wdata,
output logic [ 3*NMEM-1:0] rvfi_mem_prot,
output logic [ 6*NMEM-1:0] rvfi_mem_atop,
output logic [ 2*NMEM-1:0] rvfi_mem_memtype,
output logic [ NMEM-1 :0] rvfi_mem_dbg,
output logic [32*32-1:0] rvfi_gpr_rdata,
output logic [31:0] rvfi_gpr_rmask,
output logic [32*32-1:0] rvfi_gpr_wdata,
output logic [31:0] rvfi_gpr_wmask,
// CSRs
output logic [31:0] rvfi_csr_jvt_rmask,
output logic [31:0] rvfi_csr_jvt_wmask,
output logic [31:0] rvfi_csr_jvt_rdata,
output logic [31:0] rvfi_csr_jvt_wdata,
output logic [31:0] rvfi_csr_mstatus_rmask,
output logic [31:0] rvfi_csr_mstatus_wmask,
output logic [31:0] rvfi_csr_mstatus_rdata,
output logic [31:0] rvfi_csr_mstatus_wdata,
output logic [31:0] rvfi_csr_mstatush_rmask,
output logic [31:0] rvfi_csr_mstatush_wmask,
output logic [31:0] rvfi_csr_mstatush_rdata,
output logic [31:0] rvfi_csr_mstatush_wdata,
output logic [31:0] rvfi_csr_misa_rmask,
output logic [31:0] rvfi_csr_misa_wmask,
output logic [31:0] rvfi_csr_misa_rdata,
output logic [31:0] rvfi_csr_misa_wdata,
output logic [31:0] rvfi_csr_mie_rmask,
output logic [31:0] rvfi_csr_mie_wmask,
output logic [31:0] rvfi_csr_mie_rdata,
output logic [31:0] rvfi_csr_mie_wdata,
output logic [31:0] rvfi_csr_mtvec_rmask,
output logic [31:0] rvfi_csr_mtvec_wmask,
output logic [31:0] rvfi_csr_mtvec_rdata,
output logic [31:0] rvfi_csr_mtvec_wdata,
output logic [31:0] rvfi_csr_mtvt_rmask,
output logic [31:0] rvfi_csr_mtvt_wmask,
output logic [31:0] rvfi_csr_mtvt_rdata,
output logic [31:0] rvfi_csr_mtvt_wdata,
output logic [31:0] rvfi_csr_mcountinhibit_rmask,
output logic [31:0] rvfi_csr_mcountinhibit_wmask,
output logic [31:0] rvfi_csr_mcountinhibit_rdata,
output logic [31:0] rvfi_csr_mcountinhibit_wdata,
output logic [31:0] [31:0] rvfi_csr_mhpmevent_rmask, // 3-31 implemented
output logic [31:0] [31:0] rvfi_csr_mhpmevent_wmask,
output logic [31:0] [31:0] rvfi_csr_mhpmevent_rdata,
output logic [31:0] [31:0] rvfi_csr_mhpmevent_wdata,
output logic [31:0] rvfi_csr_mscratch_rmask,
output logic [31:0] rvfi_csr_mscratch_wmask,
output logic [31:0] rvfi_csr_mscratch_rdata,
output logic [31:0] rvfi_csr_mscratch_wdata,
output logic [31:0] rvfi_csr_mepc_rmask,
output logic [31:0] rvfi_csr_mepc_wmask,
output logic [31:0] rvfi_csr_mepc_rdata,
output logic [31:0] rvfi_csr_mepc_wdata,
output logic [31:0] rvfi_csr_mcause_rmask,
output logic [31:0] rvfi_csr_mcause_wmask,
output logic [31:0] rvfi_csr_mcause_rdata,
output logic [31:0] rvfi_csr_mcause_wdata,
output logic [31:0] rvfi_csr_mtval_rmask,
output logic [31:0] rvfi_csr_mtval_wmask,
output logic [31:0] rvfi_csr_mtval_rdata,
output logic [31:0] rvfi_csr_mtval_wdata,
output logic [31:0] rvfi_csr_mip_rmask,
output logic [31:0] rvfi_csr_mip_wmask,
output logic [31:0] rvfi_csr_mip_rdata,
output logic [31:0] rvfi_csr_mip_wdata,
output logic [31:0] rvfi_csr_mnxti_rmask,
output logic [31:0] rvfi_csr_mnxti_wmask,
output logic [31:0] rvfi_csr_mnxti_rdata,
output logic [31:0] rvfi_csr_mnxti_wdata,
output logic [31:0] rvfi_csr_mintstatus_rmask,
output logic [31:0] rvfi_csr_mintstatus_wmask,
output logic [31:0] rvfi_csr_mintstatus_rdata,
output logic [31:0] rvfi_csr_mintstatus_wdata,
output logic [31:0] rvfi_csr_mintthresh_rmask,
output logic [31:0] rvfi_csr_mintthresh_wmask,
output logic [31:0] rvfi_csr_mintthresh_rdata,
output logic [31:0] rvfi_csr_mintthresh_wdata,
output logic [31:0] rvfi_csr_mscratchcsw_rmask,
output logic [31:0] rvfi_csr_mscratchcsw_wmask,
output logic [31:0] rvfi_csr_mscratchcsw_rdata,
output logic [31:0] rvfi_csr_mscratchcsw_wdata,
output logic [31:0] rvfi_csr_mscratchcswl_rmask,
output logic [31:0] rvfi_csr_mscratchcswl_wmask,
output logic [31:0] rvfi_csr_mscratchcswl_rdata,
output logic [31:0] rvfi_csr_mscratchcswl_wdata,
output logic [31:0] rvfi_csr_tselect_rmask,
output logic [31:0] rvfi_csr_tselect_wmask,
output logic [31:0] rvfi_csr_tselect_rdata,
output logic [31:0] rvfi_csr_tselect_wdata,
output logic [ 2:0] [31:0] rvfi_csr_tdata_rmask, // 1-2 implemented
output logic [ 2:0] [31:0] rvfi_csr_tdata_wmask,
output logic [ 2:0] [31:0] rvfi_csr_tdata_rdata,
output logic [ 2:0] [31:0] rvfi_csr_tdata_wdata,
output logic [31:0] rvfi_csr_tinfo_rmask,
output logic [31:0] rvfi_csr_tinfo_wmask,
output logic [31:0] rvfi_csr_tinfo_rdata,
output logic [31:0] rvfi_csr_tinfo_wdata,
output logic [31:0] rvfi_csr_dcsr_rmask,
output logic [31:0] rvfi_csr_dcsr_wmask,
output logic [31:0] rvfi_csr_dcsr_rdata,
output logic [31:0] rvfi_csr_dcsr_wdata,
output logic [31:0] rvfi_csr_dpc_rmask,
output logic [31:0] rvfi_csr_dpc_wmask,
output logic [31:0] rvfi_csr_dpc_rdata,
output logic [31:0] rvfi_csr_dpc_wdata,
output logic [ 1:0] [31:0] rvfi_csr_dscratch_rmask, // 0-1 implemented
output logic [ 1:0] [31:0] rvfi_csr_dscratch_wmask,
output logic [ 1:0] [31:0] rvfi_csr_dscratch_rdata,
output logic [ 1:0] [31:0] rvfi_csr_dscratch_wdata,
output logic [31:0] rvfi_csr_mcycle_rmask,
output logic [31:0] rvfi_csr_mcycle_wmask,
output logic [31:0] rvfi_csr_mcycle_rdata,
output logic [31:0] rvfi_csr_mcycle_wdata,
output logic [31:0] rvfi_csr_minstret_rmask,
output logic [31:0] rvfi_csr_minstret_wmask,
output logic [31:0] rvfi_csr_minstret_rdata,
output logic [31:0] rvfi_csr_minstret_wdata,
output logic [31:0] [31:0] rvfi_csr_mhpmcounter_rmask, // 3-31 implemented
output logic [31:0] [31:0] rvfi_csr_mhpmcounter_wmask,
output logic [31:0] [31:0] rvfi_csr_mhpmcounter_rdata,
output logic [31:0] [31:0] rvfi_csr_mhpmcounter_wdata,
output logic [31:0] rvfi_csr_mcycleh_rmask,
output logic [31:0] rvfi_csr_mcycleh_wmask,
output logic [31:0] rvfi_csr_mcycleh_rdata,
output logic [31:0] rvfi_csr_mcycleh_wdata,
output logic [31:0] rvfi_csr_minstreth_rmask,
output logic [31:0] rvfi_csr_minstreth_wmask,
output logic [31:0] rvfi_csr_minstreth_rdata,
output logic [31:0] rvfi_csr_minstreth_wdata,
output logic [31:0] [31:0] rvfi_csr_mhpmcounterh_rmask, // 3-31 implemented
output logic [31:0] [31:0] rvfi_csr_mhpmcounterh_wmask,
output logic [31:0] [31:0] rvfi_csr_mhpmcounterh_rdata,
output logic [31:0] [31:0] rvfi_csr_mhpmcounterh_wdata,
output logic [31:0] rvfi_csr_cycle_rmask,
output logic [31:0] rvfi_csr_cycle_wmask,
output logic [31:0] rvfi_csr_cycle_rdata,
output logic [31:0] rvfi_csr_cycle_wdata,
output logic [31:0] rvfi_csr_instret_rmask,
output logic [31:0] rvfi_csr_instret_wmask,
output logic [31:0] rvfi_csr_instret_rdata,
output logic [31:0] rvfi_csr_instret_wdata,
output logic [31:0] [31:0] rvfi_csr_hpmcounter_rmask, // 3-31 implemented
output logic [31:0] [31:0] rvfi_csr_hpmcounter_wmask,
output logic [31:0] [31:0] rvfi_csr_hpmcounter_rdata,
output logic [31:0] [31:0] rvfi_csr_hpmcounter_wdata,
output logic [31:0] rvfi_csr_cycleh_rmask,
output logic [31:0] rvfi_csr_cycleh_wmask,
output logic [31:0] rvfi_csr_cycleh_rdata,
output logic [31:0] rvfi_csr_cycleh_wdata,
output logic [31:0] rvfi_csr_instreth_rmask,
output logic [31:0] rvfi_csr_instreth_wmask,
output logic [31:0] rvfi_csr_instreth_rdata,
output logic [31:0] rvfi_csr_instreth_wdata,
output logic [31:0] [31:0] rvfi_csr_hpmcounterh_rmask, // 3-31 implemented
output logic [31:0] [31:0] rvfi_csr_hpmcounterh_wmask,
output logic [31:0] [31:0] rvfi_csr_hpmcounterh_rdata,
output logic [31:0] [31:0] rvfi_csr_hpmcounterh_wdata,
output logic [31:0] rvfi_csr_mvendorid_rmask,
output logic [31:0] rvfi_csr_mvendorid_wmask,
output logic [31:0] rvfi_csr_mvendorid_rdata,
output logic [31:0] rvfi_csr_mvendorid_wdata,
output logic [31:0] rvfi_csr_marchid_rmask,
output logic [31:0] rvfi_csr_marchid_wmask,
output logic [31:0] rvfi_csr_marchid_rdata,
output logic [31:0] rvfi_csr_marchid_wdata,
output logic [31:0] rvfi_csr_mimpid_rmask,
output logic [31:0] rvfi_csr_mimpid_wmask,
output logic [31:0] rvfi_csr_mimpid_rdata,
output logic [31:0] rvfi_csr_mimpid_wdata,
output logic [31:0] rvfi_csr_mhartid_rmask,
output logic [31:0] rvfi_csr_mhartid_wmask,
output logic [31:0] rvfi_csr_mhartid_rdata,
output logic [31:0] rvfi_csr_mhartid_wdata,
output logic [31:0] rvfi_csr_mcounteren_rmask,
output logic [31:0] rvfi_csr_mcounteren_wmask,
output logic [31:0] rvfi_csr_mcounteren_rdata,
output logic [31:0] rvfi_csr_mcounteren_wdata,
output logic [PMP_MAX_REGIONS/4-1:0][31:0] rvfi_csr_pmpcfg_rmask,
output logic [PMP_MAX_REGIONS/4-1:0][31:0] rvfi_csr_pmpcfg_wmask,
output logic [PMP_MAX_REGIONS/4-1:0][31:0] rvfi_csr_pmpcfg_rdata,
output logic [PMP_MAX_REGIONS/4-1:0][31:0] rvfi_csr_pmpcfg_wdata,
output logic [PMP_MAX_REGIONS-1:0] [31:0] rvfi_csr_pmpaddr_rmask,
output logic [PMP_MAX_REGIONS-1:0] [31:0] rvfi_csr_pmpaddr_wmask,
output logic [PMP_MAX_REGIONS-1:0] [31:0] rvfi_csr_pmpaddr_rdata,
output logic [PMP_MAX_REGIONS-1:0] [31:0] rvfi_csr_pmpaddr_wdata,
output logic [31:0] rvfi_csr_mseccfg_rmask,
output logic [31:0] rvfi_csr_mseccfg_wmask,
output logic [31:0] rvfi_csr_mseccfg_rdata,
output logic [31:0] rvfi_csr_mseccfg_wdata,
output logic [31:0] rvfi_csr_mseccfgh_rmask,
output logic [31:0] rvfi_csr_mseccfgh_wmask,
output logic [31:0] rvfi_csr_mseccfgh_rdata,
output logic [31:0] rvfi_csr_mseccfgh_wdata,
output logic [31:0] rvfi_csr_mconfigptr_rmask,
output logic [31:0] rvfi_csr_mconfigptr_wmask,
output logic [31:0] rvfi_csr_mconfigptr_rdata,
output logic [31:0] rvfi_csr_mconfigptr_wdata,
output logic [31:0] rvfi_csr_menvcfg_rmask,
output logic [31:0] rvfi_csr_menvcfg_wmask,
output logic [31:0] rvfi_csr_menvcfg_rdata,
output logic [31:0] rvfi_csr_menvcfg_wdata,
output logic [31:0] rvfi_csr_menvcfgh_rmask,
output logic [31:0] rvfi_csr_menvcfgh_wmask,
output logic [31:0] rvfi_csr_menvcfgh_rdata,
output logic [31:0] rvfi_csr_menvcfgh_wdata,
output logic [31:0] rvfi_csr_cpuctrl_rmask,
output logic [31:0] rvfi_csr_cpuctrl_wmask,
output logic [31:0] rvfi_csr_cpuctrl_rdata,
output logic [31:0] rvfi_csr_cpuctrl_wdata,
output logic [31:0] rvfi_csr_secureseed0_rmask,
output logic [31:0] rvfi_csr_secureseed0_wmask,
output logic [31:0] rvfi_csr_secureseed0_rdata,
output logic [31:0] rvfi_csr_secureseed0_wdata,
output logic [31:0] rvfi_csr_secureseed1_rmask,
output logic [31:0] rvfi_csr_secureseed1_wmask,
output logic [31:0] rvfi_csr_secureseed1_rdata,
output logic [31:0] rvfi_csr_secureseed1_wdata,
output logic [31:0] rvfi_csr_secureseed2_rmask,
output logic [31:0] rvfi_csr_secureseed2_wmask,
output logic [31:0] rvfi_csr_secureseed2_rdata,
output logic [31:0] rvfi_csr_secureseed2_wdata,
output logic [31:0] rvfi_csr_mstateen0_rmask,
output logic [31:0] rvfi_csr_mstateen0_wmask,
output logic [31:0] rvfi_csr_mstateen0_rdata,
output logic [31:0] rvfi_csr_mstateen0_wdata,
output logic [31:0] rvfi_csr_mstateen1_rmask,
output logic [31:0] rvfi_csr_mstateen1_wmask,
output logic [31:0] rvfi_csr_mstateen1_rdata,
output logic [31:0] rvfi_csr_mstateen1_wdata,
output logic [31:0] rvfi_csr_mstateen2_rmask,
output logic [31:0] rvfi_csr_mstateen2_wmask,
output logic [31:0] rvfi_csr_mstateen2_rdata,
output logic [31:0] rvfi_csr_mstateen2_wdata,
output logic [31:0] rvfi_csr_mstateen3_rmask,
output logic [31:0] rvfi_csr_mstateen3_wmask,
output logic [31:0] rvfi_csr_mstateen3_rdata,
output logic [31:0] rvfi_csr_mstateen3_wdata,
output logic [31:0] rvfi_csr_mstateen0h_rmask,
output logic [31:0] rvfi_csr_mstateen0h_wmask,
output logic [31:0] rvfi_csr_mstateen0h_rdata,
output logic [31:0] rvfi_csr_mstateen0h_wdata,
output logic [31:0] rvfi_csr_mstateen1h_rmask,
output logic [31:0] rvfi_csr_mstateen1h_wmask,
output logic [31:0] rvfi_csr_mstateen1h_rdata,
output logic [31:0] rvfi_csr_mstateen1h_wdata,
output logic [31:0] rvfi_csr_mstateen2h_rmask,
output logic [31:0] rvfi_csr_mstateen2h_wmask,
output logic [31:0] rvfi_csr_mstateen2h_rdata,
output logic [31:0] rvfi_csr_mstateen2h_wdata,
output logic [31:0] rvfi_csr_mstateen3h_rmask,
output logic [31:0] rvfi_csr_mstateen3h_wmask,
output logic [31:0] rvfi_csr_mstateen3h_rdata,
output logic [31:0] rvfi_csr_mstateen3h_wdata
);
// Propagating from ID stage
logic [3:0] [31:0] pc_wdata;
logic [4:0] debug_mode;
logic [4:0] [ 2:0] debug_cause;
logic [4:0] instr_pmp_err;
obi_inst_req_t [4:0] instr_req;
rvfi_intr_t [4:0] in_trap;
logic [4:0] [ 4:0] rs1_addr;
logic [4:0] [ 4:0] rs2_addr;
logic [4:0] [31:0] rs1_rdata;
logic [4:0] [31:0] rs2_rdata;
logic [4:0] [ 3:0] mem_rmask;
logic [4:0] [ 3:0] mem_wmask;
// Propagate from ID stage on all suboperations.
logic [3:0] [ 4:0] rs1_addr_subop;
logic [3:0] [ 4:0] rs2_addr_subop;
logic [3:0] [31:0] rs1_rdata_subop;
logic [3:0] [31:0] rs2_rdata_subop;
logic [3:0] rs1_re_subop;
logic [3:0] rs2_re_subop;
// Remember last instruction in WB
logic [31:0] instr_rdata_wb_past;
logic [31:0] pc_wb_past;
logic [4:0] rd_addr_wb_past;
logic [31:0] rd_wdata_wb_past;
//Propagating from EX stage
obi_data_req_t ex_mem_trans;
mem_err_t [3:0] mem_err;
logic lsu_split_2nd_xfer_wb;
logic lsu_split_xfer_wb;
logic branch_taken_ex;
logic [ 3:0] rvfi_mem_mask_int;
logic [ 4:0] rd_addr_wb;
logic [31:0] rd_wdata_wb;
logic [ 4:0] rs1_addr_id;
logic [ 4:0] rs2_addr_id;
logic [31:0] rs1_rdata_id;
logic [31:0] rs2_rdata_id;
// CSR inputs in struct format
rvfi_csr_map_t rvfi_csr_rdata_d;
rvfi_csr_map_t rvfi_csr_rmask_d;
rvfi_csr_map_t rvfi_csr_wdata_d;
rvfi_csr_map_t rvfi_csr_wmask_d;
rvfi_csr_map_t rvfi_csr_rdata;
rvfi_csr_map_t rvfi_csr_rmask;
rvfi_csr_map_t rvfi_csr_wdata;
rvfi_csr_map_t rvfi_csr_wmask;
// Reads from autonomous registers propagate from EX stage
rvfi_auto_csr_map_t ex_csr_rdata;
rvfi_auto_csr_map_t ex_csr_rdata_d;
logic [31:0][31:0] csr_mhpmcounter_n_l;
logic [31:0][31:0] csr_mhpmcounter_n_h;
logic [31:0][31:0] csr_mhpmcounter_q_l;
logic [31:0][31:0] csr_mhpmcounter_q_h;
logic [31:0][31:0] csr_mhpmcounter_we_l;
logic [31:0][31:0] csr_mhpmcounter_we_h;
// Signals for special handling of performance counters
logic [31:0][31:0] mhpmcounter_l_rdata_q;
logic [31:0][31:0] mhpmcounter_l_wdata_q;
logic [31:0][31:0] mhpmcounter_h_rdata_q;
logic [31:0][31:0] mhpmcounter_h_wdata_q;
// Counter was written during WB and possibly before wb_valid
logic [31:0] mhpmcounter_l_during_wb;
logic [31:0] mhpmcounter_h_during_wb;
logic wb_valid_lastop;
logic wb_valid_subop;
logic pc_mux_debug;
logic pc_mux_dret;
logic pc_mux_exception;
logic pc_mux_interrupt;
logic pc_mux_nmi;
logic [6:0] insn_opcode;
logic [4:0] insn_rd;
logic [2:0] insn_funct3;
logic [4:0] insn_rs1;
logic [4:0] insn_rs2;
logic [6:0] insn_funct7;
logic [11:0] insn_csr;
// PCs for jumps from ID and branches from EX
logic [31:0] pc_wdata_id_jump, pc_wdata_id_jump_q;
logic [31:0] pc_wdata_ex_branch, pc_wdata_ex_branch_q;
// sub operation counter
logic [3:0] subop_cnt;
// Memory operation counter
logic [6:0] memop_cnt;
rvfi_obi_instr_t obi_instr_if;
obi_data_req_t lsu_data_trans;
logic lsu_data_trans_valid;
// Detect mret initiated CLIC pointer in WB
logic mret_ptr_wb;
// Detect a PMA error due to atomics accessing non-atomic regions
logic lsu_pma_err_atomic_ex;
// Detect PMA errors due to misaligned accesses
logic lsu_pma_err_misaligned_ex;
assign mret_ptr_wb = mret_ptr_wb_i;
assign insn_opcode = rvfi_insn[6:0];
assign insn_rd = rvfi_insn[11:7];
assign insn_funct3 = rvfi_insn[14:12];
assign insn_rs1 = rvfi_insn[19:15];
assign insn_rs2 = rvfi_insn[24:20];
assign insn_funct7 = rvfi_insn[31:25];
assign insn_csr = rvfi_insn[31:20];
assign lsu_pma_err_atomic_ex = 1'b0; // No atomics on cv32e40s
// PMA error due to misaligned accesses to I/O memory
assign lsu_pma_err_misaligned_ex = lsu_pma_err_ex_i && lsu_misaligned_ex_i && !lsu_pma_cfg_ex_i.main;
cv32e40s_rvfi_instr_obi
rvfi_instr_obi_i
(
.clk ( clk_i ),
.rst_n ( rst_ni ),
.prefetch_valid_i ( prefetch_valid_if_i ),
.prefetch_ready_i ( prefetch_ready_if_i ),
.prefetch_addr_i ( prefetch_addr_if_i ),
.prefetch_compressed_i ( prefetch_compressed_if_i ),
.kill_if_i ( ctrl_fsm_i.kill_if ),
.mpu_status_i ( mpu_status_i ),
.pmp_err_i ( instr_pmp_err_if_i ),
.prefetch_trans_valid_i ( prefetch_trans_valid_i ),
.prefetch_trans_ready_i ( prefetch_trans_ready_i ),
.prefetch_resp_valid_i ( prefetch_resp_valid_i ),
.m_c_obi_instr_if ( m_c_obi_instr_if ),
.obi_instr ( obi_instr_if )
);
cv32e40s_rvfi_data_obi
rvfi_data_obi_i
(
.clk ( clk_i ),
.rst_n ( rst_ni ),
.buffer_trans_i ( buffer_trans_ex_i ),
.buffer_trans_valid_i ( buffer_trans_valid_ex_i ),
.lsu_data_trans_o ( lsu_data_trans ),
.lsu_data_trans_valid_o ( lsu_data_trans_valid )
);
// Generate PCs for jumps and branches taken from ID and EX stages
// PCs must be kept sticky, since jumps and branches are taken in the first cycle, while the RVFI pipeline is
// only updated when the next pipeline stage is ready (e.g. when id_valid_i && ex_ready_i)
always_comb begin
// Generate PC for jumps taken from ID
pc_wdata_id_jump = pc_wdata_id_jump_q;
if (ctrl_fsm_i.pc_set) begin
if((ctrl_fsm_i.pc_mux == PC_MRET) ||
(ctrl_fsm_i.pc_mux == PC_JUMP) ||
(ctrl_fsm_i.pc_mux == PC_POINTER) ||
(ctrl_fsm_i.pc_mux == PC_TBLJUMP)) begin
pc_wdata_id_jump = branch_addr_n_i;
end
end
// Generate PC for branches taken from EX
pc_wdata_ex_branch = pc_wdata_ex_branch_q;
if (ctrl_fsm_i.pc_set) begin
if(ctrl_fsm_i.pc_mux == PC_BRANCH) begin
pc_wdata_ex_branch = branch_addr_n_i;
end
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
pc_wdata_id_jump_q <= '0;
pc_wdata_ex_branch_q <= '0;
end
else begin
pc_wdata_id_jump_q <= pc_wdata_id_jump;
pc_wdata_ex_branch_q <= pc_wdata_ex_branch;
end
end
// The pc_mux signals probe the MUX in the IF stage to extract information about events in the WB stage.
// These signals are therefore used both in the WB stage to see effects of the executed instruction (e.g. rvfi_trap), and
// in the IF stage to see the reason for executing the instruction (e.g. rvfi_intr).
assign pc_mux_interrupt = (ctrl_fsm_i.pc_mux == PC_TRAP_IRQ) || (ctrl_fsm_i.pc_mux == PC_TRAP_CLICV);
assign pc_mux_nmi = (ctrl_fsm_i.pc_mux == PC_TRAP_NMI);
assign pc_mux_debug = (ctrl_fsm_i.pc_mux == PC_TRAP_DBD);
assign pc_mux_exception = (ctrl_fsm_i.pc_mux == PC_TRAP_EXC) || (ctrl_fsm_i.pc_mux == PC_TRAP_DBE) ;
assign pc_mux_dret = (ctrl_fsm_i.pc_mux == PC_DRET);
assign branch_taken_ex = branch_in_ex_i && branch_decision_ex_i;
// Assign rvfi channels
assign rvfi_halt = 1'b0; // No instruction causing halt in cv32e40s
assign rvfi_ixl = 2'b01; // XLEN for current privilege level, must be 1(32) for RV32 systems
logic in_trap_clr;
// Clear in trap pipeline when it reaches rvfi_intr
// This is done to avoid reporting already signaled triggers as suppressed during by debug
assign in_trap_clr = wb_valid_lastop && in_trap[STAGE_WB].intr;
// Set rvfi_trap for instructions causing exception or debug entry.
rvfi_trap_t rvfi_trap_next;
// Indicate that a data transfer was blocked before reaching the bus.
logic mem_access_blocked_wb;
assign mem_access_blocked_wb = |wpt_match_wb_i ||
(mpu_status_wb_i != MPU_OK);
always_comb begin
rvfi_trap_next = '0;
if (pc_mux_debug) begin
// All debug entries will set pc_mux_debug but only synchronous debug entries will set wb_valid (and in turn rvfi_valid)
// as asynchronous entries will kill the WB stage whereas synchronous entries will not.
// Indicate that the trap is a synchronous trap into debug mode
rvfi_trap_next.debug = 1'b1;
// Special case for debug entry from debug mode caused by EBREAK as it is not captured by ctrl_fsm_i.debug_cause
rvfi_trap_next.debug_cause = (ebreak_in_wb_i && debug_mode_q_i) ? DBG_CAUSE_EBREAK : ctrl_fsm_i.debug_cause;
end
if (pc_mux_exception) begin
// Indicate synchronous (non-debug entry) trap
rvfi_trap_next.exception = 1'b1;
rvfi_trap_next.exception_cause = ctrl_fsm_i.csr_cause.exception_code[5:0]; // All synchronous exceptions fit in lower 6 bits
rvfi_trap_next.clicptr = clic_ptr_wb_i;
// Separate exception causes with the same ecseption cause code
case (ctrl_fsm_i.csr_cause.exception_code)
EXC_CAUSE_INSTR_FAULT : begin
rvfi_trap_next.cause_type = instr_pmp_err[STAGE_WB] ? 2'h1 : 2'h0;
end
EXC_CAUSE_BREAKPOINT : begin
// Todo: Add support for trigger match exceptions when implemented in rtl
end
EXC_CAUSE_LOAD_FAULT : begin
rvfi_trap_next.cause_type = mem_err[STAGE_WB];
end
EXC_CAUSE_STORE_FAULT : begin
rvfi_trap_next.cause_type = mem_err[STAGE_WB];
end
default : begin
// rvfi_trap_next.cause_type is only set for exception codes that can have multiple causes
end
endcase // case (ctrl_fsm_i.csr_cause.exception_code)
end
// Check for single step debug entry, need to include the actual debug_cause_n, as single step has the lowest priority
// to enter debug and any higher priority cause could be active at the same time.
if((pending_single_step_i && single_step_allowed_i) && (debug_cause_n_i == DBG_CAUSE_STEP)) begin
// For single step debug entry, the pipeline is not halted. This causes wb_valid to become 1 in the cycle
// before DEBUG_TAKEN is entered, as opposed to other debug causes which halt the entire pipeline.
// To pick up the rvfi_trap.debug for single step one can thus not rely on 'pc_mux_debug' but must check the
// relevant signals within the controller FSM that causes a single step transition into DEBUG_TAKEN.
rvfi_trap_next.debug = 1'b1;
rvfi_trap_next.debug_cause = DBG_CAUSE_STEP;
// In the case of an exception in WB and pending single step, both the exception and the debug flag will be set
end
// Check for etrigger debug entry, need to include the actual debug_cause_n, as etrigger has lower priority
// to enter debug than for instance external debug request.
if((etrigger_in_wb_i && single_step_allowed_i) && (debug_cause_n_i == DBG_CAUSE_TRIGGER)) begin
// For etrigger debug entry, the pipeline is not halted. This causes wb_valid to become 1 in the cycle
// before DEBUG_TAKEN is entered, as opposed to other debug causes which halt the entire pipeline.
// To pick up the rvfi_trap.debug for etrigger one can thus not rely on 'pc_mux_debug' but must check the
// relevant signals within the controller FSM that causes a etrigger transition into DEBUG_TAKEN.
rvfi_trap_next.debug = 1'b1;
rvfi_trap_next.debug_cause = DBG_CAUSE_TRIGGER;
// For etrigger, both exception and debug flag is set.
end
// Set trap bit if there is an exception or debug entry
rvfi_trap_next.trap = rvfi_trap_next.exception || rvfi_trap_next.debug;
end
logic dummy_suppressed_intr;
// Sticky rvfi_intr bit to allow signalling rvfi_intr from ignored dummy instructions
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
dummy_suppressed_intr <= 1'b0;
end else begin
if (wb_valid_i) begin
if (is_dummy_instr_wb_i) begin
dummy_suppressed_intr <= in_trap[STAGE_WB] || dummy_suppressed_intr;
end else begin
// Only clear the flag once an instruction fully completes.
// Otherwise the first operation of a sequence could clear the flag, causing the
// rvfi_valid following (wb_valid && last_op) to miss its rvfi_intr.
if (last_op_wb_i) begin
dummy_suppressed_intr <= 1'b0;
end
end
end
end
end
// All instructions retire when wb_valid is high and it either is a last_op or an abort_op.
// CLIC pointers are excluded if they do not raise an exception.
// Faulted CLIC pointer fetches are reported with rvfi_valid and rvfi_trap.clicptr==1.
// CLIC pointers that are a result of an mret (instr_meta.mret_ptr) finish the sequence mret->ptr, and shall raise rvfi_valid_* to retire the mret.
assign wb_valid_subop = wb_valid_i && !(clic_ptr_wb_i && !pc_mux_exception);
assign wb_valid_lastop = wb_valid_i && (last_op_wb_i || abort_op_wb_i) && !(clic_ptr_wb_i && !pc_mux_exception);
// Return byte-mask for bytes that would be part of the 2nd transfer in a split transfer.
// Note that this function does not take transfer size into account, it only indicates
// the bytes that could be part of the 2nd transfer.
function automatic logic [3:0] split_2nd_mask(logic [1:0] addr_lsb);
logic [3:0] mask = '0;
case(addr_lsb[1:0])
2'b00 : mask = 4'b0000; // No bytes would come from the 2nd transfer
2'b01 : mask = 4'b1000; // Byte 3 would come from the 2nd transfer
2'b10 : mask = 4'b1100; // Byte 2,3 would come from the 2nd transfer
2'b11 : mask = 4'b1110; // Byte 1,2,3 would com from the 2nd transfer
endcase
return mask;
endfunction : split_2nd_mask
// Pipeline stage model //
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
pc_wdata <= '0;
in_trap <= '0;
debug_mode <= '0;
debug_cause <= '0;
instr_pmp_err <= '0;
instr_req <= '0;
rs1_addr <= '0;
rs2_addr <= '0;
rs1_rdata <= '0;
rs2_rdata <= '0;
mem_rmask <= '0;
mem_wmask <= '0;
ex_mem_trans <= '0;
mem_err <= {4{MEM_ERR_IO_ALIGN}};
ex_csr_rdata <= '0;
rvfi_dbg <= '0;
rvfi_dbg_mode <= '0;
rvfi_valid <= 1'b0;
rvfi_order <= '0;
rvfi_insn <= '0;
rvfi_instr_prot <= '0;
rvfi_instr_memtype <= '0;
rvfi_instr_dbg <= '0;
rvfi_pc_rdata <= '0;
rvfi_pc_wdata <= '0;
rvfi_trap <= '0;
rvfi_intr <= 1'b0;
rvfi_mode <= 2'b11; // Reset value of rvfi_mode is being used as 'previous privilege level'
rvfi_rd_addr <= '0;
rvfi_rd_wdata <= '0;
rvfi_csr_rdata <= '0;
rvfi_csr_wdata <= '0;
rvfi_csr_wmask <= '0;
rvfi_rs1_addr <= '0;
rvfi_rs2_addr <= '0;
rvfi_rs1_rdata <= '0;
rvfi_rs2_rdata <= '0;
rvfi_mem_addr <= '0;
rvfi_mem_rmask <= '0;
rvfi_mem_rdata <= '0;
rvfi_mem_wmask <= '0;
rvfi_mem_wdata <= '0;
rvfi_mem_prot <= '0;
rvfi_mem_memtype <= '0;
rvfi_mem_atop <= '0;