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vax_cpu.c
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vax_cpu.c
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/* vax_cpu.c: VAX CPU
Copyright (c) 1998-2012, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
cpu VAX central processor
20-Sep-11 MP Fixed idle conditions for various versions of Ultrix,
Quasijarus-4.3BSD, NetBSD and OpenBSD.
Note: Since NetBSD and OpenBSD are still actively
developed operating systems, new versions of
these OSes are moving targets with regard to
providing idle detection. At this time, recent versions
of OpenBSD have veered from the traditional OS idle
approach taken in the other BSD derived OSes.
Determining a reasonable idle detection pattern does
not seem possible for these versions.
13-Sep-11 RMS Fixed XFC, BPT to clear PSL<tp> before exception
(Camiel Vanderhoeven)
23-Mar-11 RMS Revised for new idle design (Mark Pizzolato)
05-Jan-11 MP Added Asynch I/O support
24-Apr-10 RMS Added OLDVMS idle timer option
Fixed bug in SET CPU IDLE
21-May-08 RMS Removed inline support
28-May-08 RMS Inlined instruction prefetch, physical memory routines
13-Aug-07 RMS Fixed bug in read access g-format indexed specifiers
28-Apr-07 RMS Removed clock initialization
29-Oct-06 RMS Added idle support
22-May-06 RMS Fixed format error in CPU history (Peter Schorn)
10-May-06 RMS Added -kesu switches for virtual addressing modes
Fixed bugs in examine virtual
Rewrote history function for greater usability
Fixed bug in reported VA on faulting cross-page write
02-May-06 RMS Fixed fault cleanup to clear PSL<tp>
Fixed ADAWI r-mode to preserve dst<31:16>
Fixed ACBD/G to test correct operand
Fixed access checking on modify-class specifiers
Fixed branch displacements in history buffer
(Tim Stark)
17-Nov-05 RMS Fixed CVTfi with integer overflow to trap if PSW<iv> set
13-Nov-05 RMS Fixed breakpoint test with 64b addresses
25-Oct-05 RMS Removed cpu_extmem
22-Sep-05 RMS Fixed declarations (Sterling Garwood)
16-Aug-05 RMS Fixed C++ declaration and cast problems
13-Jan-05 RMS Fixed initial state of cpu_extmem
06-Nov-04 RMS Added =n to SHOW HISTORY
30-Sep-04 RMS Added octaword specifier decodes and instructions
Moved model-specific routines to system module
02-Sep-04 RMS Fixed bug in EMODD/G, second word of quad dst not probed
28-Jun-04 RMS Fixed bug in DIVBx, DIVWx (Peter Trimmel)
18-Apr-04 RMS Added octaword macros
25-Jan-04 RMS Removed local debug logging support
RMS,MP Added extended physical memory support
31-Dec-03 RMS Fixed bug in set_cpu_hist
21-Dec-03 RMS Added autoconfiguration controls
29-Oct-03 RMS Fixed WriteB declaration (Mark Pizzolato)
23-Sep-03 RMS Revised instruction history for dynamic sizing
17-May-03 RMS Fixed operand order in EMODx
23-Apr-03 RMS Revised for 32b/64b t_addr
05-Jan-02 RMS Added memory size restore support
25-Dec-02 RMS Added instruction history (Mark Pizzolato)
29-Sep-02 RMS Revised to build dib_tab dynamically
14-Jul-02 RMS Added halt to console, infinite loop detection (Mark Pizzolato)
02-May-02 RMS Fixed bug in indexed autoincrement register logging
30-Apr-02 RMS Added TODR powerup routine
18-Apr-02 RMS Cleanup ambiguous signed left shifts
15-Apr-02 RMS Fixed bug in CASEL condition codes
The register state for the VAX is:
R[0:15] general registers
PSL<31:0> processor status longword
TP<30> trace pending
FPD<27> first part done
IS<26> interrupt stack
CM<25:24> current mode
PM<23:22> previous mode
IPL<20:16> interrupt priority level
PSW<15:0> non-privileged processor status word
DV<7> decimal overflow trap enable
FU<6> floating underflow fault enable
IV<5> integer overflow trap enable
T<4> trace trap enable
CC<3:0> condition codes
SCBB system control block base
PCBB process control block base
SBR system page table base
SLR system page table length
P0BR process region 0 page table base
P0LR process region 0 page table length
P1BR process region 1 page table base
P1LR process region 1 page table length
SIRR/SISR software interrupt request/summary register
ASTLVL AST level register
The VAX has a variable length instruction format with up to six operands:
opcode byte
operand 1 specifier
:
operand n specifier
Each operand specifier is a byte consisting of an addressing mode, a
register, and possibly 1-8 bytes of extension:
number name extension mnemonic operation
0-3 short literal - #n op <- specifier
4 index - [Rn] index by Rn
5 register - Rn op <- Rn
6 register def - (Rn) op <- M[Rn]
7 autodecrement - -(Rn) Rn <- Rn - length
op <- M[Rn]
8 autoincrement - (Rn)+ op <- M[Rn]
Rn <- Rn + length
9 auto deferred - @(Rn)+ op <- M[M[Rn]]
Rn <- Rn + 4
A byte displ byte d d(Rn) op <- M[Rn + sxt.d]
B byte displ def byte d @d(Rn) op <- M[M[Rn + sxt.d]]
C word displ word d d(Rn) op <- M[Rn + sxt.d]
D word displ def word d @d(Rn) op <- M[M[Rn + sxt.d]]
E long displ long d d(Rn) op <- M[Rn + d]
F long displ def long d @d(Rn) op <- M[M[Rn + d]]
When the general register is the PC, certain modes are forbidden, and
others have special interpretations:
4F index fault
5F register fault
6F register def fault
7F autodecrement fault
8F immediate 1-8B #imm op <- imm
9 absolute 4B @#imm op <- M[imm]
A byte relative byte d d(Rn) op <- M[PC + sxt.d]
B byte rel def byte d @d(Rn) op <- M[M[PC + sxt.d]]
C word relative word d d(Rn) op <- M[PC + sxt.d]
D word rel def word d @d(Rn) op <- M[M[PC + sxt.d]]
E long relative long d d(Rn) op <- M[PC + d]
F long rel def long d @d(Rn) op <- M[M[PC + d]]
This routine is the instruction decode routine for the VAX. It
is called from the simulator control program to execute instructions
in simulated memory, starting at the simulated PC. It runs until an
enabled exception is encountered.
General notes:
1. Traps and interrupts. Variable trpirq microencodes the outstanding
trap request (if any) and the level of the highest outstanding
interrupt (if any).
2. Interrupt requests are maintained in the int_req array, one word per
interrupt level, one bit per device.
3. Adding I/O devices. These modules must be modified:
vax_defs.h add device address and interrupt definitions
vax_sys.c add sim_devices table entry
*/
/* Definitions */
#include "vax_defs.h"
#define OP_MEM -1
#define UNIT_V_CONH (UNIT_V_UF + 0) /* halt to console */
#define UNIT_V_MSIZE (UNIT_V_UF + 1) /* dummy */
#define UNIT_CONH (1u << UNIT_V_CONH)
#define UNIT_MSIZE (1u << UNIT_V_MSIZE)
#define GET_CUR acc = ACC_MASK (PSL_GETCUR (PSL))
#define OPND_SIZE 16
#define INST_SIZE 52
#define op0 opnd[0]
#define op1 opnd[1]
#define op2 opnd[2]
#define op3 opnd[3]
#define op4 opnd[4]
#define op5 opnd[5]
#define op6 opnd[6]
#define op7 opnd[7]
#define op8 opnd[8]
#define CHECK_FOR_PC if (rn == nPC) \
RSVD_ADDR_FAULT
#define CHECK_FOR_SP if (rn >= nSP) \
RSVD_ADDR_FAULT
#define CHECK_FOR_AP if (rn >= nAP) \
RSVD_ADDR_FAULT
#define WRITE_B(r) if (spec > (GRN | nPC)) \
Write (va, r, L_BYTE, WA); \
else R[rn] = (R[rn] & ~BMASK) | ((r) & BMASK)
#define WRITE_W(r) if (spec > (GRN | nPC)) \
Write (va, r, L_WORD, WA); \
else R[rn] = (R[rn] & ~WMASK) | ((r) & WMASK)
#define WRITE_L(r) if (spec > (GRN | nPC)) \
Write (va, r, L_LONG, WA); \
else R[rn] = (r)
#define WRITE_Q(rl,rh) if (spec > (GRN | nPC)) { \
if ((Test (va + 7, WA, &mstat) >= 0) || \
(Test (va, WA, &mstat) < 0)) \
Write (va, rl, L_LONG, WA); \
Write (va + 4, rh, L_LONG, WA); \
} \
else { \
if (rn >= nSP) \
RSVD_ADDR_FAULT; \
R[rn] = rl; \
R[rn + 1] = rh; \
}
#define HIST_MIN 64
#define HIST_MAX 250000
typedef struct {
double time;
int32 iPC;
int32 PSL;
int32 opc;
uint8 inst[INST_SIZE];
int32 opnd[OPND_SIZE];
} InstHistory;
uint32 *M = NULL; /* memory */
int32 R[16]; /* registers */
int32 STK[5]; /* stack pointers */
int32 PSL; /* PSL */
int32 SCBB = 0; /* SCB base */
int32 PCBB = 0; /* PCB base */
int32 P0BR = 0; /* P0 mem mgt */
int32 P0LR = 0;
int32 P1BR = 0; /* P1 mem mgt */
int32 P1LR = 0;
int32 SBR = 0; /* S0 mem mgt */
int32 SLR = 0;
int32 SISR; /* swre int req */
int32 ASTLVL; /* AST level */
int32 mapen; /* map enable */
int32 pme; /* perf mon enable */
int32 trpirq; /* trap/intr req */
int32 in_ie = 0; /* in exc, int */
int32 recq[6]; /* recovery queue */
int32 recqptr; /* recq pointer */
int32 hlt_pin = 0; /* HLT pin intr */
int32 mem_err = 0;
int32 crd_err = 0;
int32 p1 = 0, p2 = 0; /* fault parameters */
int32 fault_PC; /* fault PC */
int32 pcq_p = 0; /* PC queue ptr */
int32 badabo = 0;
int32 cpu_astop = 0;
int32 mchk_va, mchk_ref; /* mem ref param */
int32 ibufl, ibufh; /* prefetch buf */
int32 ibcnt, ppc; /* prefetch ctl */
uint32 cpu_idle_mask = VAX_IDLE_VMS; /* idle mask */
uint32 cpu_idle_type = 1; /* default VMS */
jmp_buf save_env;
REG *pcq_r = NULL; /* PC queue reg ptr */
int32 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
InstHistory *hst = NULL; /* instruction history */
int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
int32 hst_switches; /* history option switches */
FILE *hst_log; /* history log file */
int32 hst_log_p; /* history last log written pointer */
int32 step_out_nest_level = 0; /* step to call return - nest level */
const uint32 byte_mask[33] = { 0x00000000,
0x00000001, 0x00000003, 0x00000007, 0x0000000F,
0x0000001F, 0x0000003F, 0x0000007F, 0x000000FF,
0x000001FF, 0x000003FF, 0x000007FF, 0x00000FFF,
0x00001FFF, 0x00003FFF, 0x00007FFF, 0x0000FFFF,
0x0001FFFF, 0x0003FFFF, 0x0007FFFF, 0x000FFFFF,
0x001FFFFF, 0x003FFFFF, 0x007FFFFF, 0x00FFFFFF,
0x01FFFFFF, 0x03FFFFFF, 0x07FFFFFF, 0x0FFFFFFF,
0x1FFFFFFF, 0x3FFFFFFF, 0x7FFFFFFF, 0xFFFFFFFF
};
const uint32 byte_sign[33] = { 0x00000000,
0x00000001, 0x00000002, 0x00000004, 0x00000008,
0x00000010, 0x00000020, 0x00000040, 0x00000080,
0x00000100, 0x00000200, 0x00000400, 0x00000800,
0x00001000, 0x00002000, 0x00004000, 0x00008000,
0x00010000, 0x00020000, 0x00040000, 0x00080000,
0x00100000, 0x00200000, 0x00400000, 0x00800000,
0x01000000, 0x02000000, 0x04000000, 0x08000000,
0x10000000, 0x20000000, 0x40000000, 0x80000000
};
const uint32 align[4] = {
0xFFFFFFFF, 0x00FFFFFF, 0x0000FFFF, 0x000000FF
};
/* External and forward references */
extern t_stat build_dib_tab (void);
extern UNIT rom_unit, nvr_unit;
extern int32 sys_model;
extern int32 op_ashq (int32 *opnd, int32 *rh, int32 *flg);
extern int32 op_emul (int32 mpy, int32 mpc, int32 *rh);
extern int32 op_ediv (int32 *opnd, int32 *rh, int32 *flg);
extern int32 op_bb_n (int32 *opnd, int32 acc);
extern int32 op_bb_x (int32 *opnd, int32 newb, int32 acc);
extern int32 op_extv (int32 *opnd, int32 vfldrp1, int32 acc);
extern int32 op_ffs (uint32 fld, int32 size);
extern void op_insv (int32 *opnd, int32 vfldrp1, int32 acc);
extern int32 op_call (int32 *opnd, t_bool gs, int32 acc);
extern int32 op_ret (int32 acc);
extern int32 op_insque (int32 *opnd, int32 acc);
extern int32 op_remque (int32 *opnd, int32 acc);
extern int32 op_insqhi (int32 *opnd, int32 acc);
extern int32 op_insqti (int32 *opnd, int32 acc);
extern int32 op_remqhi (int32 *opnd, int32 acc);
extern int32 op_remqti (int32 *opnd, int32 acc);
extern void op_pushr (int32 *opnd, int32 acc);
extern void op_popr (int32 *opnd, int32 acc);
extern int32 op_movc (int32 *opnd, int32 opc, int32 acc);
extern int32 op_cmpc (int32 *opnd, int32 opc, int32 acc);
extern int32 op_locskp (int32 *opnd, int32 opc, int32 acc);
extern int32 op_scnspn (int32 *opnd, int32 opc, int32 acc);
extern int32 op_chm (int32 *opnd, int32 cc, int32 opc);
extern int32 op_rei (int32 acc);
extern void op_ldpctx (int32 acc);
extern void op_svpctx (int32 acc);
extern int32 op_probe (int32 *opnd, int32 opc);
extern int32 op_mtpr (int32 *opnd);
extern int32 op_mfpr (int32 *opnd);
extern int32 op_movfd (int32 val);
extern int32 op_movg (int32 val);
extern int32 op_mnegfd (int32 val);
extern int32 op_mnegg (int32 val);
extern int32 op_cmpfd (int32 h1, int32 l1, int32 h2, int32 l2);
extern int32 op_cmpg (int32 h1, int32 l1, int32 h2, int32 l2);
extern int32 op_cvtifdg (int32 val, int32 *rh, int32 opc);
extern int32 op_cvtfdgi (int32 *opnd, int32 *flg, int32 opc);
extern int32 op_cvtdf (int32 *opnd);
extern int32 op_cvtgf (int32 *opnd);
extern int32 op_cvtfg (int32 *opnd, int32 *rh);
extern int32 op_cvtgh (int32 *opnd, int32 *hflt);
extern int32 op_addf (int32 *opnd, t_bool sub);
extern int32 op_addd (int32 *opnd, int32 *rh, t_bool sub);
extern int32 op_addg (int32 *opnd, int32 *rh, t_bool sub);
extern int32 op_mulf (int32 *opnd);
extern int32 op_muld (int32 *opnd, int32 *rh);
extern int32 op_mulg (int32 *opnd, int32 *rh);
extern int32 op_divf (int32 *opnd);
extern int32 op_divd (int32 *opnd, int32 *rh);
extern int32 op_divg (int32 *opnd, int32 *rh);
extern int32 op_emodf (int32 *opnd, int32 *intgr, int32 *flg);
extern int32 op_emodd (int32 *opnd, int32 *rh, int32 *intgr, int32 *flg);
extern int32 op_emodg (int32 *opnd, int32 *rh, int32 *intgr, int32 *flg);
extern void op_polyf (int32 *opnd, int32 acc);
extern void op_polyd (int32 *opnd, int32 acc);
extern void op_polyg (int32 *opnd, int32 acc);
extern int32 op_cmode (int32 cc);
extern int32 op_cis (int32 *opnd, int32 cc, int32 opc, int32 acc);
extern int32 op_octa (int32 *opnd, int32 cc, int32 opc, int32 acc, int32 spec, int32 va);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 Test (uint32 va, int32 acc, int32 *status);
extern int32 BadCmPSL (int32 newpsl);
extern int32 eval_int (void);
extern int32 get_vector (int32 lvl);
extern void set_map_reg (void);
extern void rom_wr_B (int32 pa, int32 val);
extern int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta);
extern const uint16 drom[NUM_INST][MAX_SPEC + 1];
extern t_stat cpu_boot (int32 unitno, DEVICE *dptr);
extern int32 con_halt (int32 code, int32 cc);
t_stat cpu_reset (DEVICE *dptr);
t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs);
t_stat cpu_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat cpu_show_virt (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat cpu_set_idle (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat cpu_show_idle (FILE *st, UNIT *uptr, int32 val, void *desc);
const char *cpu_description (DEVICE *dptr);
int32 cpu_get_vsw (int32 sw);
static SIM_INLINE int32 get_istr (int32 lnt, int32 acc);
int32 ReadOcta (int32 va, int32 *opnd, int32 j, int32 acc);
t_bool cpu_show_opnd (FILE *st, InstHistory *h, int32 line);
t_stat cpu_show_hist_records (FILE *st, t_bool do_header, int32 start, int32 count);
t_stat cpu_idle_svc (UNIT *uptr);
void cpu_idle (void);
/* CPU data structures
cpu_dev CPU device descriptor
cpu_unit CPU unit
cpu_reg CPU register list
cpu_mod CPU modifier list
*/
UNIT cpu_unit = {
UDATA (&cpu_idle_svc, UNIT_FIX|UNIT_BINK, INITMEMSIZE)
};
const char *psl_modes[] = {"K", "E", "S", "U"};
BITFIELD psl_bits[] = {
BIT(C), /* Carry */
BIT(V), /* Overflow */
BIT(Z), /* Zero */
BIT(N), /* Negative */
BIT(T), /* trace */
BIT(IV), /* Integer overflow */
BIT(FU), /* Floating underflow */
BIT(DV), /* Decimal overflow */
BITNCF(8), /* MBZ */
BITFFMT(IPL,5,%d), /* IPL */
BITNCF(1), /* MBZ */
BITFNAM(PRVMOD,2,psl_modes), /* Previous Access Mode */
BITFNAM(CURMOD,2,psl_modes), /* Current Access Mode */
BIT(IS), /* Interrupt Stack */
BIT(FPD), /* First Part Done */
BITNCF(2), /* MBZ */
BIT(TP), /* Trace Pending */
BIT(CM), /* Compatibility Mode */
ENDBITS
};
REG cpu_reg[] = {
{ HRDATAD (PC, R[nPC], 32, "program counter") },
{ HRDATAD (R0, R[0], 32, "General Purpose Register 0") },
{ HRDATAD (R1, R[1], 32, "General Purpose Register 1") },
{ HRDATAD (R2, R[2], 32, "General Purpose Register 2") },
{ HRDATAD (R3, R[3], 32, "General Purpose Register 3") },
{ HRDATAD (R4, R[4], 32, "General Purpose Register 4") },
{ HRDATAD (R5, R[5], 32, "General Purpose Register 5") },
{ HRDATAD (R6, R[6], 32, "General Purpose Register 6") },
{ HRDATAD (R7, R[7], 32, "General Purpose Register 7") },
{ HRDATAD (R8, R[8], 32, "General Purpose Register 8") },
{ HRDATAD (R9, R[9], 32, "General Purpose Register 9") },
{ HRDATAD (R10, R[10], 32, "General Purpose Register 10") },
{ HRDATAD (R11, R[11], 32, "General Purpose Register 11") },
{ HRDATAD (R12, R[12], 32, "General Purpose Register 12") },
{ HRDATAD (R13, R[13], 32, "General Purpose Register 13") },
{ HRDATAD (R14, R[14], 32, "General Purpose Register 14") },
{ HRDATAD (AP, R[nAP], 32, "Alias for R12") },
{ HRDATAD (FP, R[nFP], 32, "Alias for R13") },
{ HRDATAD (SP, R[nSP], 32, "Alias for R14") },
{ HRDATADF(PSL, PSL, 32, "processor status longword", psl_bits) },
{ HRDATAD (CC, PSL, 4, "condition codes, PSL<3:0>") },
{ HRDATAD (KSP, KSP, 32, "kernel stack pointer") },
{ HRDATAD (ESP, ESP, 32, "executive stack pointer") },
{ HRDATAD (SSP, SSP, 32, "supervisor stack pointer") },
{ HRDATAD (USP, USP, 32, "user stack pointer") },
{ HRDATAD (IS, IS, 32, "interrupt stack pointer") },
{ HRDATAD (SCBB, SCBB, 32, "system control block base") },
{ HRDATAD (PCBB, PCBB, 32, "process control block base") },
{ HRDATAD (P0BR, P0BR, 32, "P0 base register") },
{ HRDATAD (P0LR, P0LR, 22, "P0 length register") },
{ HRDATAD (P1BR, P1BR, 32, "P1 base register") },
{ HRDATAD (P1LR, P1LR, 22, "P1 length register") },
{ HRDATAD (SBR, SBR, 32, "system base register") },
{ HRDATAD (SLR, SLR, 22, "system length register") },
{ HRDATAD (SISR, SISR, 16, "software interrupt summary register") },
{ HRDATAD (ASTLVL, ASTLVL, 4, "AST level register") },
{ FLDATAD (MAPEN, mapen, 0, "memory management enable") },
{ FLDATAD (PME, pme, 0, "performance monitor enable") },
{ HRDATAD (TRPIRQ, trpirq, 8, "trap/interrupt pending") },
{ FLDATAD (CRDERR, crd_err, 0, "correctible read data error flag") },
{ FLDATAD (MEMERR, mem_err, 0, "memory error flag") },
{ FLDATA (HLTPIN, hlt_pin, 0) },
{ HRDATA (IDLE_MASK, cpu_idle_mask, 16), REG_HIDDEN },
{ DRDATA (IDLE_INDX, cpu_idle_type, 4), REG_HRO },
{ DRDATA (IDLE_ENAB, sim_idle_enab, 4), REG_HRO },
{ BRDATAD (PCQ, pcq, 16, 32, PCQ_SIZE, "PC prior to last PC change or interrupt;"), REG_RO+REG_CIRC },
{ HRDATA (PCQP, pcq_p, 6), REG_HRO },
{ HRDATA (BADABO, badabo, 32), REG_HRO },
{ HRDATAD (WRU, sim_int_char, 8, "interrupt character") },
{ HRDATA (MODEL, sys_model, 32), REG_HRO },
{ NULL }
};
MTAB cpu_mod[] = {
{ UNIT_CONH, 0, "HALT to SIMH", "SIMHALT", NULL, NULL, NULL, "Set HALT to trap to simulator" },
{ UNIT_CONH, UNIT_CONH, "HALT to console", "CONHALT", NULL, NULL, NULL, "Set HALT to trap to console ROM" },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE={VMS|ULTRIX|NETBSD|OPENBSD|ULTRIXOLD|OPENBSDOLD|QUASIJARUS|32V|ELN|ALL}", &cpu_set_idle, &cpu_show_idle, NULL, "Display idle detection mode" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL, NULL, "Disables idle detection" },
MEM_MODIFIERS, /* Model specific memory modifiers from vaxXXX_defs.h */
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
&cpu_set_hist, &cpu_show_hist, NULL, "Displays instruction history" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
NULL, &cpu_show_virt, NULL, "show translation for address arg in KESU mode" },
CPU_MODEL_MODIFIERS, /* Model specific cpu modifiers from vaxXXX_defs.h */
{ 0 }
};
DEBTAB cpu_deb[] = {
{ "INTEXC", LOG_CPU_I },
{ "REI", LOG_CPU_R },
{ "CONTEXT", LOG_CPU_P },
{ "EVENT", SIM_DBG_EVENT },
{ "ACTIVATE", SIM_DBG_ACTIVATE },
{ "ASYNCH", SIM_DBG_AIO_QUEUE },
{ NULL, 0 }
};
DEVICE cpu_dev = {
"CPU", &cpu_unit, cpu_reg, cpu_mod,
1, 16, 32, 1, 16, 8,
&cpu_ex, &cpu_dep, &cpu_reset,
&cpu_boot, NULL, NULL,
NULL, DEV_DYNM | DEV_DEBUG, 0,
cpu_deb, &cpu_set_size, NULL, &cpu_help, NULL, NULL,
&cpu_description
};
t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc)
{
fprintf (st, "model=");
return cpu_print_model (st);
}
const char *cpu_description (DEVICE *dptr)
{
static char buf[80];
uint32 min_mem = 4096, max_mem = 0;
MTAB *mptr;
for (mptr = dptr->modifiers; mptr && (mptr->mask != 0); mptr++) {
if (mptr->valid != &cpu_set_size)
continue;
if ((mptr->match >> 20) < min_mem)
min_mem = (mptr->match >> 20);
if ((mptr->match >> 20) > max_mem)
max_mem = (mptr->match >> 20);
}
sprintf (buf, "VAX CPU with %dMB-%dMB of memory", (int)min_mem, (int)max_mem);
return buf;
}
t_stat sim_instr (void)
{
volatile int32 opc = 0, cc; /* used by setjmp */
volatile int32 acc; /* set by setjmp */
int abortval;
t_stat r;
if ((r = build_dib_tab ()) != SCPE_OK) /* build, chk dib_tab */
return r;
if ((PSL & PSL_MBZ) || /* validate PSL<mbz> */
((PSL & PSL_CM) && BadCmPSL (PSL)) || /* validate PSL<cm> */
((PSL_GETCUR (PSL) != KERN) && /* esu => is, ipl = 0 */
(PSL & (PSL_IS|PSL_IPL))) ||
((PSL & PSL_IS) && ((PSL & PSL_IPL) == 0))) /* is => ipl > 0 */
return SCPE_STOP;
cc = PSL & CC_MASK; /* split PSL */
PSL = PSL & ~CC_MASK;
in_ie = 0; /* not in exc */
set_map_reg (); /* set map reg */
GET_CUR; /* set access mask */
SET_IRQL; /* eval interrupts */
FLUSH_ISTR; /* clear prefetch */
abortval = setjmp (save_env); /* set abort hdlr */
if (abortval > 0) { /* sim stop? */
PSL = PSL | cc; /* put PSL together */
pcq_r->qptr = pcq_p; /* update pc q ptr */
if (hst_log) { /* auto logging history? */
cpu_show_hist_records (hst_log, FALSE, hst_log_p, (hst_p < hst_log_p) ? hst_lnt - (hst_log_p - hst_p) : hst_p - hst_log_p);
hst_log_p = hst_p; /* record everything logged */
}
return abortval; /* return to SCP */
}
else if (abortval < 0) { /* mm or rsrv or int */
int32 i, delta;
if ((PSL & PSL_FPD) == 0) { /* FPD? no recovery */
for (i = 0; i < recqptr; i++) { /* unwind inst */
int32 rrn, rlnt;
rrn = RQ_GETRN (recq[i]); /* recover reg # */
rlnt = DR_LNT (RQ_GETLNT (recq[i])); /* recovery lnt */
if (recq[i] & RQ_DIR)
R[rrn] = R[rrn] - rlnt;
else R[rrn] = R[rrn] + rlnt;
}
}
PSL = PSL & ~PSL_TP; /* clear <tp> */
recqptr = 0; /* clear queue */
delta = PC - fault_PC; /* save delta PC */
SETPC (fault_PC); /* restore PC */
switch (-abortval) { /* case on abort code */
case SCB_RESIN: /* rsrv inst fault */
case SCB_RESAD: /* rsrv addr fault */
case SCB_RESOP: /* rsrv opnd fault */
if (in_ie) /* in exc? panic */
ABORT (STOP_INIE);
cc = intexc (-abortval, cc, 0, IE_EXC); /* take exception */
GET_CUR; /* PSL<cur> changed */
break;
case SCB_CMODE: /* comp mode fault */
case SCB_ARITH: /* arithmetic fault */
if (in_ie) /* in exc? panic */
ABORT (STOP_INIE);
cc = intexc (-abortval, cc, 0, IE_EXC); /* take exception */
GET_CUR;
in_ie = 1;
Write (SP - 4, p1, L_LONG, WA); /* write arith param */
SP = SP - 4;
in_ie = 0;
break;
case SCB_ACV: /* ACV fault */
case SCB_TNV: /* TNV fault */
if (in_ie) { /* in exception? */
if (PSL & PSL_IS) /* on is? panic */
ABORT (STOP_INIE);
cc = intexc (SCB_KSNV, cc, 0, IE_SVE); /* ksnv */
GET_CUR;
}
else {
cc = intexc (-abortval, cc, 0, IE_EXC); /* take exception */
GET_CUR;
in_ie = 1;
Write (SP - 8, p1, L_LONG, WA); /* write mm params */
Write (SP - 4, p2, L_LONG, WA);
SP = SP - 8;
in_ie = 0;
}
break;
case SCB_MCHK: /* machine check */
cc = machine_check (p1, opc, cc, delta); /* system specific */
in_ie = 0;
GET_CUR; /* PSL<cur> changed */
break;
case 1: /* interrupt */
break; /* just proceed */
default: /* other */
badabo = abortval; /* save code */
ABORT (STOP_UNKABO); /* panic */
} /* end case */
} /* end else */
/* Main instruction loop */
for ( ;; ) {
int32 spec, disp, rn, index, numspec;
int32 vfldrp1, brdisp, flg, mstat;
int32 i, j, r, rh, temp;
uint32 va, iad;
int32 opnd[OPND_SIZE]; /* operand queue */
if (cpu_astop) {
cpu_astop = 0;
ABORT (SCPE_STOP);
}
fault_PC = PC;
recqptr = 0; /* clr recovery q */
AIO_CHECK_EVENT; /* queue async events */
if (sim_interval <= 0) { /* chk clock queue */
temp = sim_process_event ();
if (temp)
ABORT (temp);
SET_IRQL; /* update interrupts */
}
/* Test for non-instruction dispatches, in SRM order
- trap or interrupt (trpirq != 0)
- PSL<tp> set
If any of these conditions are met, re-dispatch; otherwise,
set PSL<tp> from PSL<t>.
*/
if (trpirq) { /* trap or interrupt? */
if ((temp = GET_TRAP (trpirq))) { /* trap? */
cc = intexc (SCB_ARITH, cc, 0, IE_EXC); /* take, clear trap */
GET_CUR; /* set cur mode */
in_ie = 1;
Write (SP - 4, temp, L_LONG, WA); /* write parameter */
SP = SP - 4;
in_ie = 0;
}
else if ((temp = GET_IRQL (trpirq))) { /* interrupt? */
int32 vec;
if (temp == IPL_HLTPIN) { /* console halt? */
hlt_pin = 0; /* clear intr */
trpirq = 0; /* clear everything */
cc = con_halt (CON_HLTPIN, cc); /* invoke firmware */
continue; /* continue */
}
else if (temp >= IPL_HMIN) /* hardware req? */
vec = get_vector (temp); /* get vector */
else if (temp > IPL_SMAX)
ABORT (STOP_UIPL);
else {
vec = SCB_IPLSOFT + (temp << 2);
SISR = SISR & ~(1u << temp);
}
if (vec) /* take intr */
cc = intexc (vec, cc, temp, IE_INT);
GET_CUR; /* set cur mode */
}
else trpirq = 0; /* clear everything */
SET_IRQL; /* eval interrupts */
continue;
}
if (PSL & (PSL_CM|PSL_TP|PSW_T)) { /* PSL event? */
if (PSL & PSL_TP) { /* trace trap? */
PSL = PSL & ~PSL_TP; /* clear <tp> */
cc = intexc (SCB_TP, cc, 0, IE_EXC); /* take trap */
GET_CUR; /* set cur mode */
continue;
}
if (PSL & PSW_T) /* if T, set TP */
PSL = PSL | PSL_TP;
if (PSL & PSL_CM) { /* compat mode? */
cc = op_cmode (cc); /* exec instr */
continue; /* skip fetch */
}
} /* end PSL event */
if (sim_brk_summ &&
sim_brk_test ((uint32) PC, SWMASK ('E'))) { /* breakpoint? */
ABORT (STOP_IBKPT); /* stop simulation */
}
sim_interval = sim_interval - 1; /* count instr */
GET_ISTR (opc, L_BYTE); /* get opcode */
if (opc == 0xFD) { /* 2 byte op? */
GET_ISTR (opc, L_BYTE); /* get second byte */
opc = opc | 0x100; /* flag */
}
numspec = drom[opc][0]; /* get # specs */
if (PSL & PSL_FPD) {
if ((numspec & DR_F) == 0)
RSVD_INST_FAULT;
}
else {
numspec = numspec & DR_NSPMASK; /* get # specifiers */
/* Specifier flows. Operands are parsed and placed into queue opnd.
r.bwl opnd[j] = value of operand
r.q opnd[j:j+1] = value of operand
r.o opnd[j:j+3] = value of operand
a.bwlqo opnd[j] = address of operand
m.bwl opnd[j] = value of operand
m.q opnd[j:j+1] = value of operand
m.o opnd[j:j+3] = value of operand
w.bwlqo opnd[j] = register/memory flag
opnd[j+1] = memory address
For the last memory specifier, the specifier is in spec, the register
number is in rn, and the effective address is in va. Modify specifiers
(always last) can test spec > reg+PC, as short literal are illegal for
modifiers specifiers, and final index specifiers are always illegal.
*/
for (i = 1, j = 0; i <= numspec; i++) { /* loop thru specs */
disp = drom[opc][i]; /* get dispatch */
if (disp >= BB) {
GET_ISTR (brdisp, DR_LNT (disp & 1));
break;
}
GET_ISTR (spec, L_BYTE); /* get spec byte */
rn = spec & RGMASK; /* get reg # */
disp = (spec & ~RGMASK) | disp; /* merge w dispatch */
switch (disp) { /* dispatch spec */
/* Short literal - only read access permitted */
case SH0|RB: case SH0|RW: case SH0|RL:
case SH1|RB: case SH1|RW: case SH1|RL:
case SH2|RB: case SH2|RW: case SH2|RL:
case SH3|RB: case SH3|RW: case SH3|RL:
opnd[j++] = spec;
break;
case SH0|RQ: case SH1|RQ: case SH2|RQ: case SH3|RQ:
opnd[j++] = spec;
opnd[j++] = 0;
break;
case SH0|RO: case SH1|RO: case SH2|RO: case SH3|RO:
opnd[j++] = spec;
opnd[j++] = 0;
opnd[j++] = 0;
opnd[j++] = 0;
break;
case SH0|RF: case SH1|RF: case SH2|RF: case SH3|RF:
opnd[j++] = (spec << 4) | 0x4000;
break;
case SH0|RD: case SH1|RD: case SH2|RD: case SH3|RD:
opnd[j++] = (spec << 4) | 0x4000;
opnd[j++] = 0;
break;
case SH0|RG: case SH1|RG: case SH2|RG: case SH3|RG:
opnd[j++] = (spec << 1) | 0x4000;
opnd[j++] = 0;
break;
case SH0|RH: case SH1|RH: case SH2|RH: case SH3|RH:
opnd[j++] = ((spec & 0x7) << 29) | (0x4000 | ((spec >> 3) & 0x7));
opnd[j++] = 0;
opnd[j++] = 0;
opnd[j++] = 0;
break;
/* Register */
case GRN|RB: case GRN|MB:
CHECK_FOR_PC;
opnd[j++] = R[rn] & BMASK;
break;
case GRN|RW: case GRN|MW:
CHECK_FOR_PC;
opnd[j++] = R[rn] & WMASK;
break;
case GRN|VB:
vfldrp1 = R[(rn + 1) & RGMASK];
case GRN|WB: case GRN|WW: case GRN|WL: case GRN|WQ: case GRN|WO:
opnd[j++] = rn;
case GRN|RL: case GRN|RF: case GRN|ML:
CHECK_FOR_PC;
opnd[j++] = R[rn];
break;
case GRN|RQ: case GRN|RD: case GRN|RG: case GRN|MQ:
CHECK_FOR_SP;
opnd[j++] = R[rn];
opnd[j++] = R[rn + 1];
break;
case GRN|RO: case GRN|RH: case GRN|MO:
CHECK_FOR_AP;
opnd[j++] = R[rn];
opnd[j++] = R[rn + 1];
opnd[j++] = R[rn + 2];
opnd[j++] = R[rn + 3];
break;
/* Register deferred, autodecrement */
case RGD|VB:
case RGD|WB: case RGD|WW: case RGD|WL: case RGD|WQ: case RGD|WO:
opnd[j++] = OP_MEM;
case RGD|AB: case RGD|AW: case RGD|AL: case RGD|AQ: case RGD|AO:
CHECK_FOR_PC;
va = opnd[j++] = R[rn];
break;
case ADC|VB:
case ADC|WB: case ADC|WW: case ADC|WL: case ADC|WQ: case ADC|WO:
opnd[j++] = OP_MEM;
case ADC|AB: case ADC|AW: case ADC|AL: case ADC|AQ: case ADC|AO:
CHECK_FOR_PC;
va = opnd[j++] = R[rn] = R[rn] - DR_LNT (disp);
recq[recqptr++] = RQ_REC (disp, rn);
break;
case ADC|RB: case ADC|RW: case ADC|RL: case ADC|RF:
R[rn] = R[rn] - (DR_LNT (disp));
recq[recqptr++] = RQ_REC (disp, rn);
case RGD|RB: case RGD|RW: case RGD|RL: case RGD|RF:
CHECK_FOR_PC;
opnd[j++] = Read (va = R[rn], DR_LNT (disp), RA);
break;
case ADC|RQ: case ADC|RD: case ADC|RG:
R[rn] = R[rn] - 8;
recq[recqptr++] = RQ_REC (disp, rn);
case RGD|RQ: case RGD|RD: case RGD|RG:
CHECK_FOR_PC;
opnd[j++] = Read (va = R[rn], L_LONG, RA);
opnd[j++] = Read (R[rn] + 4, L_LONG, RA);
break;
case ADC|RO: case ADC|RH:
R[rn] = R[rn] - 16;
recq[recqptr++] = RQ_REC (disp, rn);
case RGD|RO: case RGD|RH:
CHECK_FOR_PC;
j = ReadOcta (va = R[rn], opnd, j, RA);
break;
case ADC|MB: case ADC|MW: case ADC|ML:
R[rn] = R[rn] - (DR_LNT (disp));
recq[recqptr++] = RQ_REC (disp, rn);
case RGD|MB: case RGD|MW: case RGD|ML:
CHECK_FOR_PC;
opnd[j++] = Read (va = R[rn], DR_LNT (disp), WA);
break;
case ADC|MQ:
R[rn] = R[rn] - 8;
recq[recqptr++] = RQ_REC (disp, rn);
case RGD|MQ:
CHECK_FOR_PC;
opnd[j++] = Read (va = R[rn], L_LONG, WA);
opnd[j++] = Read (R[rn] + 4, L_LONG, WA);
break;
case ADC|MO:
R[rn] = R[rn] - 16;
recq[recqptr++] = RQ_REC (disp, rn);
case RGD|MO:
CHECK_FOR_PC;
j = ReadOcta (va = R[rn], opnd, j, WA);
break;
/* Autoincrement */
case AIN|VB:
case AIN|WB: case AIN|WW: case AIN|WL: case AIN|WQ: case AIN|WO:
/* CHECK_FOR_PC; */
opnd[j++] = OP_MEM;
case AIN|AB: case AIN|AW: case AIN|AL: case AIN|AQ: case AIN|AO:
va = opnd[j++] = R[rn];
if (rn == nPC) {
if (DR_LNT (disp) >= L_QUAD) {
GET_ISTR (temp, L_LONG);
GET_ISTR (temp, L_LONG);
if (DR_LNT (disp) == L_OCTA) {
GET_ISTR (temp, L_LONG);
GET_ISTR (temp, L_LONG);
}
}
else GET_ISTR (temp, DR_LNT (disp));
}
else {
R[rn] = R[rn] + DR_LNT (disp);
recq[recqptr++] = RQ_REC (disp, rn);
}
break;
case AIN|RB: case AIN|RW: case AIN|RL: case AIN|RF:
va = R[rn];
if (rn == nPC) {
GET_ISTR (opnd[j++], DR_LNT (disp));
}
else {
opnd[j++] = Read (R[rn], DR_LNT (disp), RA);
R[rn] = R[rn] + DR_LNT (disp);
recq[recqptr++] = RQ_REC (disp, rn);
}
break;
case AIN|RQ: case AIN|RD: case AIN|RG:
va = R[rn];
if (rn == nPC) {
GET_ISTR (opnd[j++], L_LONG);
GET_ISTR (opnd[j++], L_LONG);
}
else {
opnd[j++] = Read (va, L_LONG, RA);
opnd[j++] = Read (va + 4, L_LONG, RA);
R[rn] = R[rn] + 8;
recq[recqptr++] = RQ_REC (disp, rn);
}
break;
case AIN|RO: case AIN|RH:
va = R[rn];
if (rn == nPC) {
GET_ISTR (opnd[j++], L_LONG);
GET_ISTR (opnd[j++], L_LONG);
GET_ISTR (opnd[j++], L_LONG);
GET_ISTR (opnd[j++], L_LONG);
}
else {
j = ReadOcta (va, opnd, j, RA);
R[rn] = R[rn] + 16;
recq[recqptr++] = RQ_REC (disp, rn);
}