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0001-imx7d-2nd-ethernet-support_update_20200218.patch
136 lines (130 loc) · 5.27 KB
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0001-imx7d-2nd-ethernet-support_update_20200218.patch
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diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index d9526853bdc0..73d759ecc461 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -154,6 +154,10 @@
status = "okay";
};
+&fec2 {
+ status = "okay";
+};
+
&i2c4 {
status = "okay";
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index 4a1ef3f83faf..edc1d2a66b75 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -131,6 +131,38 @@
fsl,magic-packet;
};
+&fec2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_enet2>;
+ pinctrl-1 = <&pinctrl_enet2_sleep>;
+ clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
+ <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>,
+ <&clks IMX7D_ENET2_REF_ROOT_DIV>;
+ assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
+ <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>, <50000000>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ phy-supply = <®_LDO1>;
+ fsl,magic-packet;
+
+ fsl,mii-exclusive;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
@@ -360,8 +392,8 @@
&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
- &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;
+ pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
+ &pinctrl_gpio5 &pinctrl_gpio7>;
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
@@ -380,9 +412,7 @@
MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
- MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
- MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
@@ -390,15 +420,10 @@
MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
- MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
- MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
- MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
- MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
- MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
@@ -507,7 +532,39 @@
>;
};
- pinctrl_ecspi3_cs: ecspi3-cs-grp {
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x73
+ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x73
+ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x73
+ MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x73
+
+ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x73
+ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x73
+ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x73
+ MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x40000073
+ MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x3
+ MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x3
+ >;
+ };
+
+ pinctrl_enet2_sleep: enet2sleepgrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0
+ MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0
+ MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0
+ MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0
+
+ MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x0
+ MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x0
+ MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0
+ MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x0
+ MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x0
+ MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0
+ >;
+ };
+
+ pinctrl_ecspi3_cs: ecspi3-cs-grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
>;