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LVDS line mapping #13
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This can be solved by removing questionable object from #11 and using those lines as LVDS1. |
USB line on the CPCIS backplane is used for LVDS as well. In case of the adapter, the only reason to have such assembly option is when we have FPGA and want to use MGT instead. |
But I don't want to have assembly option on the adapter. The point is that current design is incompatible with DIOT Controller. LVDS1 is routed to DIOT Controller's MGTx_RX that has no assembly variant on controller that would enable driving this line with IO pins. |
Once we switch the controller to LVDS mode, it can be bi-dir. |
You mean MGT RX line can be treated as IO? Then what for is an assembly variant for TX? |
Let's start from the beginning. When we started the unification of SInara and DIOT, one issue arrived. |
with such an approach, we would use the Sinara assembly variant now, but later on, get rid of variants once the universal backplane is done. |
btw, it looks like Schroff (nVent) will also offer DIOT crates. |
Wow, do you have any official information? |
Coming back to LVDS lines. Take a look at the table:
LVDS 1 on adapter has no way to be connected to normal IO on DIOT controller. It can only be connected to MGT RX. In current configuration, when using DIOT controller, we won't have 16 LVDS lines. At the same time, one line (DIFF_2 in DIOT backplane nomenclature) is wasted for some questionable pads... |
they delivered prototypes to CERN |
OK, so it seems that LVDS1 must be connected to these pads. No idea why Michal connected it in such a way. |
MGT_Rx
(CPCIsPE_Rx
). This is incompatible with DIOT Controller, where non-MGT connection was foreseen only forPE_Tx
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