dmastream.c~

/*******************************************************************
 * This is a test program for the C interface of the 
 * pciDriver library adaptaded to the VC707 Dev Board.
 * 
 * $Revision: 1.2 $
 * $Date: 2013-02-25 $
 * 
 *******************************************************************/

/*******************************************************************
 * Change History:
 * 
 * $Log: not supported by cvs2svn $
 * Revision 1.1  2006-10-16 16:56:56  marcus
 * Initial version. Tests the C interface of the library.
 *
 *******************************************************************/

#include "/root/Documents/spaiagua/Swinger/pcie_dev_driver/pciDriver/include/lib/pciDriver.h"
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>

#define MAX_KBUF (8*1024*1024)
#define MAX_UBUF (64*1024*1024)

/* Address ranges from system.mhs */

#define PCIE_BASE 		0x0
#define DMA_BASE 		0x1000
#define BRAM_BASE 		0x2000
#define SUMVEC_BASE0 		0x3000 	  
#define SUMVEC_BASE1 		0x4000


#define AXI_PCIE 		0x0
#define BRAM_ABS_BASE		0x80004000


/* Indexes based on 32-bit (4 bytes) accesses */

#define PCIE_INDEX 		(PCI_BASE/0x4)
#define DMA_INDEX 		(DMA_BASE/0x4)
#define BRAM_INDEX			(BRAM_BASE/0x4)
#define SUMVEC_INDEX0		(SUMVEC_BASE0/0x4)
#define SUMVEC_INDEX1		(SUMVEC_BASE1/0x4)

/* DMA Controller Register Space */
#define MM2S_DMACR		0x0 	// MM2S DMA Control Register
#define MM2S_DMASR		0x4 	// MM2S DMA Status Register
#define MM2S_CURDESC		0x8 	// MM2S DMA Current Descriptor Pointer
#define MM2S_TAILDESC		0x10 	// MM2S DMA Tail Descriptor Pointer
#define S2MM_DMACR		0x30
#define S2MM_DMASR		0x34
#define S2MM_CURDESC		0x38
#define S2MM_TAILDESC		0x40

/* Bit Masks */
#define DMACR_RS		0x1		// Run/Stop control bit (R/W)
#define DMACR_RESET		0x4		// Soft Reset bit (R/W)
#define DMACR_KEYHOLE		0x8		// Keyhole read (R/W)
#define DMACR_IOC_IrqEn		0x1000		// Interrupt on Complete (IOC) Interrupt Enable (R/W)
#define DMACR_Dly_IrqEn		0x2000		// Interrupt on Delay Timer Interrupt Enable (R/W)
#define DMACR_Err_IrqEn		0x4000		// Interrupt on Error Interrupt Enable (R/W)
#define DMACR_IRQThreshold	0xFF0000	// Interrupt Threshold value - 8bits - (R/W)
#define DMACR_IRQDelay		0xFF000000	// Interrupt Delay Time Out - 8bits - (R/W)

#define DMASR_HALTED		0x1		// Run/Stop state of the DMA channel (RO)
#define DMASR_IDLE		0x2		// Idle state of the DMA channel (RO)
#define DMASR_SGINCLD		0x8		// Scatter Gather Engine Included (RO)
#define DMASR_DMAINTERR		0x10 		// DMA Internal Error (RO)
#define DMASR_DMASLVERR		0x20 		// DMA Slave Error (RO)
#define DMASR_DMADECERR		0x40 		// DMA Decode Error (RO)
#define DMASR_SGINTERR		0x100 		// Scatter Gather Internal Error (RO)
#define DMASR_SGSLVERR		0x200 		// Scatter Gather Slave Error (RO)
#define DMASR_SGDECERR		0x400 		// Scatter Gather Decode Error (RO)
#define DMASR_IOC_IRQ		0x1000 		// Interrupt on Complete (R/W)
#define DMASR_DLY_IRQ		0x2000 		// Interrupt on Delay (R/W)
#define DMASR_ERR_IRQ		0x4000 		// Interrupt on Error (R/W)
#define DMASR_IRQTHRESHOLDSTS	0xFF0000 		// Interrupt Threshold Status - 8bits - (RO)
#define DMASR_IRQDELAYSTS	0xFF000000 		// Interrupt Delay Time Status - 8bits - (RO)

#define CURDESC_PTR		0xFFFFFFC0	// Current Descriptor Pointer - 26 bits - (RO) - Only written when DMACR.RS=0 and DMASR.Halted=1
#define TAILDESC_PTR		0xFFFFFFC0	// Tail Descriptor Pointer - 26 bits - (R/W)

/* Scatter Gather Descriptors */
#define NXTDESC			0x0		// Next descriptor pointer
#define BUFFER_ADDRESS		0x8		// Buffer address
#define CONTROL			0x18		// Control
#define STATUS			0x1C		// Status

/* Bit Masks */
#define NXTDESC_PTR		0xFFFFFFC0	// Descriptor pointer mask - 26 bits

#define BUFFADDR		0xFFFFFFFF	// Buffer address mask

#define CONTROL_BUFFLEN		0x7FFFFF	// Buffer length - 23 bits
#define CONTROL_TXEOF		0x4000000	// Transmit End Of Frame - 1 bit - MM2S ONLY
#define CONTROL_TXSOF		0x8000000	// Transmit Start Of Frame - 1 bit - MM2S ONLY

#define STATUS_TRANSF		0x7FFFFF	// Transferred bytes for this descriptor - 23 bits
#define STATUS_RXEOF		0x4000000	// End of Frame - 1 bit - S2MM ONLY
#define STATUS_RXSOF		0x8000000	// Start of Frame - 1 bit - S2MM ONLY
#define STATUS_DMAINTERR	0x10000000	// DMA Internal Error - 1 bit
#define STATUS_DMASLVERR	0x20000000	// DMA Slave Error - 1 bit
#define STATUS_DMADECERR	0x40000000	// DMA Decode Error - 1 bit
#define STATUS_CMPLT		0x80000000	// Completed transfer

/* AXI Bridge for PCI Express Address Translation */
#define AXIBAR2PCIEBAR0		0x20C		// AXIBAR2PCIEBAR0 register offset

#define PCIE2AXI		0x80000000	// PCI to AXI address mapping

#define AXI2PCIE_MASK		0xFF000000	// AXI can address 16MB (0x00FFFFFF)

/* transaction FROM device goes as follows :
 * 1. allocate buffer in kernel space for the data to transfer
 * 2. map the buffer to bus address space
 * 3. setup an entry in avalon-mm-to-pcie addr translation table
 * 4. setup dma transaction: src, dest, length
 * 5. init completion variable
 * 6. enable irq in the pcie bridge
 * 7. fire the transfer, wait for completion
 * 8. in the interrupt, determine
 *    the avalon interrupt # and complete appropriate compl var.
 * 9. disable irq in the pcie bridge
 * a. confirm the dma status
 * b. unmap dma buffer
 * c. copy the data from kernel space to user space
 * d. free kernel-space buffer
 */

/* transaction TO device goes as follows :
 * 1. allocate buffer in kernel space for the data to transfer
 * 2. copy the data from user space to kernel space
 * 3. map the buffer to bus address space
 * 4. init completion variable
 * 5. setup an entry in avalon-mm-to-pcie addr translation table
 * 6. setup dma transaction: src, dest, length
 * 7. enable irq in the pcie bridge
 * 8. fire the transfer, wait for completion
 * 9. in the interrupt, determine
 *    the avalon interrupt # and complete appropriate compl var.
 * a. disable irq in the pcie bridge
 * b. confirm the dma status
 * c. unmap dma buffer
 * d. free kernel-space buffer
 */


void dumpBRAM(void *bar)
{
 int i;
 
 printf("Dumping BRAM contents\n"); 
 
 for(i=0;i<4096/4;i++){
  printf("%08x ",((unsigned int*)bar)[BRAM_INDEX + i]); 
 }
}

void resetBRAM(void *bar)
{
 int i;
 
 printf("Resetting BRAM contents\n");
 
  for(i=0;i<4096/4;i++){
  ((unsigned int*)bar)[BRAM_INDEX + i] = 0; 
 }
}

/* Returns the AXI address corresponding to the PCIE space address
 * pci_addr - The address referred to the PCIE side
 */
unsigned int getAXIaddr(unsigned int pci_addr)
{
 return pci_addr + PCIE2AXI; 
}

/* Set address translation from AXI to PCIe address space, by finding a base that makes all SG Entries addressable by the AXI bus 
* umem - user memory mapped to the PCI device
* umem_tr - user memory with addresses referred to the AXI side
* base_ptr - base address for the AXI2PCIE translation
*/
int addrTranslation(pd_umem_t *umem, pd_umem_t **umem_tr, unsigned int *base_ptr)
{
  unsigned int base_addr;
  int i;

  if (umem->nents == 0){
     printf("Error: SG list is empty\n");
     return -1;
  } 

  // Create a umem structure with translated addresses
  *umem_tr = (pd_umem_t*)malloc(sizeof(pd_umem_t));
  if(*umem_tr == NULL){
     printf("Error: Could not malloc umem structure\n");
     return(-1);
  }

  (*umem_tr)->vma = umem->vma;
  (*umem_tr)->size = umem->size;
  (*umem_tr)->handle_id = umem->handle_id;
  (*umem_tr)->nents = umem->nents;
  (*umem_tr)->pci_handle = umem->pci_handle;
  
  (*umem_tr)->sg = (pd_umem_sgentry_t*)malloc(sizeof(pd_umem_sgentry_t)*umem->nents);
  if((*umem_tr)->sg == NULL){
     printf("Error: Could not malloc sgentry structure\n");
     return(-1);
  }

  // Get base address from first SG descriptor
  base_addr = (umem->sg[0]).addr & AXI2PCIE_MASK;

// All the remaining descriptors must fit within the addressable space of the AXI bus...
  for(i = 0; i < umem->nents; i++){
	if((umem->sg[i]).addr & AXI2PCIE_MASK != base_addr){
	   printf("Error: Could not map descriptors into addressable range of the AXI bus\n");
	   return(-1);
	}

	// Save translated address
	((*umem_tr)->sg[i]).addr = (umem->sg[i]).addr - base_addr;
	((*umem_tr)->sg[i]).size = (umem->sg[i]).size;
  }

  *base_ptr = base_addr;
  return(0);  
}

/* Setup an entry in the AXI2PCIEbar register
 * base_ptr - pointer to the base of the memory range that will hold the transferred data
 * bar_ptr - pointer to the mapped BAR0 of the PCIE core
 */
int setAXI2PCIEbar(unsigned int base_ptr, void *bar_ptr)
{
  unsigned int prev_ptr;
  
  prev_ptr = ((unsigned int*)bar_ptr)[AXIBAR2PCIEBAR0/4];
  // Print current AXI2PCIE Vector for debugging
  printf("Previous AXI2PCIE Vector: %08x\n",prev_ptr);
  
  if(prev_ptr == base_ptr)
    return 0;
  
  // Set new AXI2PCIE Vector
  printf("Setting AXI2PCIE Vector to: %08x\n",base_ptr);
  ((unsigned int*)bar_ptr)[AXIBAR2PCIEBAR0/4] = base_ptr;
  
  // Check if vector changed successfuly
  if(base_ptr != ((unsigned int*)bar_ptr)[AXIBAR2PCIEBAR0/4]){
      printf("AXI2PCIE Vector configuration failed.\n");
      return -1;
  }
  
  return 0;
}

int checkDMAerrors(void *bar_ptr, unsigned int STATUSREG)
{
 unsigned int status_reg;
 int ret = 0; 
 
 status_reg = ((unsigned int*)bar_ptr)[DMA_INDEX + (STATUSREG/4)];
 
 if(status_reg & DMASR_DMAINTERR){
   printf("Error: DMA Internal Error\n");
   ret = -1; 
 }
 if(status_reg & DMASR_SGSLVERR){
   printf("Error: DMA Slave Error\n");
  ret = -1; 
 }
 if(status_reg & DMASR_DMADECERR){
   printf("Error: DMA Decode Error\n");
  ret = -1; 
 }
 if(status_reg & DMASR_SGINTERR){
   printf("Error: DMA Scatter Gather Internal Error\n");
  ret = -1; 
 }
 if(status_reg & DMASR_SGSLVERR){
   printf("Error: DMA Scatter Gather Slave Error\n"); ret = -1; 
 }
 if(status_reg & DMASR_SGDECERR){
   printf("Error: DMA Scatter Gather Decode Error\n");
  ret = -1; 
 }
  
  return ret;
}

void MM2Sreset(void *bar_ptr)
{
  unsigned int read_reset;
  
 // Set soft reset bit
 ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] | DMACR_RESET;
 
 // Check if reset is done
 do{
   read_reset = ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] & DMACR_RESET;
   usleep(10); // Sleep for 10 us
   
}
 while(read_reset != 0);
  
}

void S2MMreset(void *bar_ptr)
{
  unsigned int read_reset;
  
 // Set soft reset bit
 ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] | DMACR_RESET;
 
 // Check if reset is done
 do{
   read_reset = ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] & DMACR_RESET;
   usleep(10); // Sleep for 10 us
   
}
 while(read_reset != 0);
  
}

/* Write a DMA descriptor to BRAM
 * bar_ptr - pointer to the mapped BAR0 of the PCIE core
 * cur_desc - location of BRAM on which the current descriptor must be written to
 * first - first descriptor in the chain
 * last - indicates if it is the last descriptor in the chain
 * buff_addr - address of the buffer associated with this descriptor
 * buff_len - length in bytes of the buffer
 */
void write_desc(void *bar_ptr, unsigned int cur_desc, int first, int last, unsigned int buff_addr, unsigned int buff_len)
{
  unsigned int write_nxt, ctl_reg;
  
  if(!last)
  	write_nxt = (cur_desc + 0x40); // Write next descriptor pointer (absolute address)
  else
	write_nxt = cur_desc;

  write_nxt = getAXIaddr(write_nxt);
  ((unsigned int*)bar_ptr)[(cur_desc/4) + (NXTDESC/4)] = write_nxt;
  
  ((unsigned int*)bar_ptr)[(cur_desc/4) + (BUFFER_ADDRESS/4)] = buff_addr;
  
  // Write Control Register
  ctl_reg = 0;
  ctl_reg = buff_len;
  if(first)
    ctl_reg = ctl_reg | CONTROL_TXSOF; // Set Start of Frame to 1
  if(last)
    ctl_reg = ctl_reg | CONTROL_TXEOF; // and End of Frame to 1 because a signle frame will be transmitted per descriptor
  
  ((unsigned int*)bar_ptr)[(cur_desc/4) + (CONTROL/4)] = ctl_reg;
}

/* Setup SG Desriptors for a DMA transfer
 * 
 */
int setupSGDesc(pd_umem_t *umem, void *bar_ptr, unsigned int base_loc, unsigned int *tail_desc)
{
  unsigned int next_desc, buff_addr, buff_len;
  int i,last = 0;
  
  if(base_loc < BRAM_BASE || base_loc > BRAM_BASE + 0x1000){
      printf("Error: Base location for descriptor ring must be within the BRAM Adress Space\n");
      return -1;
  }
  
  if(base_loc % 0x40 != 0){
      printf("Error: Base location must be 16-word aligned\n");
      return -1;
  }
  
  printf("Number of SG entries: %d\n", umem->nents );
		
	// Create descriptors and write them to the BRAM memory
	next_desc = (unsigned int)base_loc;
	for(i=0;i<umem->nents;i++) {
		printf("Descriptor %d: %08x - %08x\n", i, (umem->sg[i]).addr, (umem->sg[i]).size);
		
		buff_addr = (umem->sg[i]).addr;
		buff_len = (umem->sg[i]).size;
		
		if(buff_len >= 0x800000){
		    printf("Error: Buffer is larger than 23 bits. Aborting\n");
		    return -1;
		}
		
		// Save the location of the tail descriptor
		if(i == (umem->nents - 1)){
		  *tail_desc = next_desc;
		  last = 1;
		}

                write_desc(bar_ptr, next_desc, (i==0), last, buff_addr, buff_len);
		
		next_desc += + 0x40; // Next descriptor is placed 16 words after current one
	}

  return 0;  
}

int startDMAsend(void *bar_ptr, unsigned int cur_desc, unsigned int tail_desc)
{
  unsigned int read_status;
  
    //0. Check if DMA engine is still running
     if(!(((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMASR/4)] & DMASR_HALTED)){
	printf("Error: MM2S channel is still running. Current transfer will be aborted\n");
	//return -1;
    }
    
    // Stop the MM2S channel by setting run/stop bit to 0
    ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] & ~DMACR_RS;
    
    //1. Write absolute address of the starting descriptor to the DMA controller
    ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_CURDESC/4)] = getAXIaddr(cur_desc);
    
    //2. Start the MM2S channel running by setting run/stop bit to 1
    ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] | DMACR_RS;
    
    // DMASR.Halted bit should deassert
    do{
      read_status = ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMASR/4)] & DMASR_HALTED;
      usleep(10); // wait for 10 us
    }while(read_status != 0);
    
    printf("MM2S channel is running\n");
    
    //3. Optionally enable interrupts
    ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] | DMACR_IOC_IrqEn;
    ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] | DMACR_Err_IrqEn;

    
    // Write 0x1 to the IRQThreshold
    ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] & ~DMACR_IRQThreshold;
    ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] | (0x1 << 16);    
    
    //4. Write an absolute address to the tail descriptor register
    tail_desc = getAXIaddr(tail_desc);
    ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_TAILDESC/4)] = tail_desc;
    printf("Tail descriptor register MM2S: %08x\n",tail_desc);
    
    return 0;
}

int startDMArecv(void *bar_ptr, unsigned int cur_desc, unsigned int tail_desc)
{
  unsigned int read_status;
  
    //0. Check if DMA engine is still running
     if(!(((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMASR/4)] & DMASR_HALTED)){
	printf("Error: S2MM channel is still running. Current transfer will be aborted\n");
	//return -1;
    }
    
    // Stop the S2MM channel by setting run/stop bit to 0
    ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] & ~DMACR_RS;
    
    //1. Write absolute address of the starting descriptor to the DMA controller
    cur_desc = getAXIaddr(cur_desc);
    ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_CURDESC/4)] = cur_desc;
    printf("Setting current descriptor on S2MM to: %08x\n",cur_desc);
    
    //2. Start the S2MM channel running by setting run/stop bit to 1
    ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] | DMACR_RS;
    
    // DMASR.Halted bit should deassert
    do{
      read_status = ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMASR/4)] & DMASR_HALTED;
      usleep(10); // sleep for 10 us
    }while(read_status != 0);
    
    printf("S2MM channel is running\n");
    
    //3. Optionally enable interrupts
    ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] | DMACR_IOC_IrqEn;
    ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] | DMACR_Err_IrqEn;

    // Write 0x1 to the IRQThreshold
    ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] & ~DMACR_IRQThreshold;
    ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] | (0x1 << 16);
    
    //4. Write an absolute address to the tail descriptor register
    tail_desc = getAXIaddr(tail_desc);
    ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_TAILDESC/4)] = tail_desc;
   
    printf("S2MM Tail descriptor register: %08x\n", tail_desc);
 
    return 0;
}


int checkSendCompletion(void *bar_ptr,unsigned int desc_base)
{
  unsigned int status_reg;
  
  //dumpBRAM(bar_ptr);
  // Check for errors
  if(checkDMAerrors(bar_ptr, MM2S_DMASR) < 0){
      printf("Resetting MM2S channel\n");
      MM2Sreset(bar_ptr);
      return -1;
  }
 
  printf("Current descriptor being worked on: %08x\n",((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_CURDESC/4)]);
 
   // Check if DMA Channel is Idle
  do{
    status_reg = ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMASR/4)] & DMASR_IDLE;
    usleep(10);
//	printf("status_reg: %08x\n");
  }while(status_reg != DMASR_IDLE);
  
  printf("MM2S channel is idle\n");
  
  
  // Currently just checks transmission of first descriptor
  status_reg = ((unsigned int*)bar_ptr)[(desc_base/4) + (STATUS/4)];

  printf("Bytes transferred for first descriptor: %08x\n",status_reg & STATUS_TRANSF);

  if(status_reg & STATUS_CMPLT)
    printf("Descriptor transfer completed successfuly\n");
  else{
    printf("Error: Could not complete descriptor transfer\n");
    return -1;
  } 
  
   // Stop the MM2S channel by setting run/stop bit to 0
    ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMACR/4)] & ~DMACR_RS;

  return 0;
}

int checkRecvCompletion(void *bar_ptr,unsigned int desc_base)
{
  unsigned int status_reg;
  
  // Check for errors
  if(checkDMAerrors(bar_ptr, S2MM_DMASR) < 0){
      printf("Resetting S2MM channel\n");
      S2MMreset(bar_ptr);
      return -1;
  }

  printf("Current descriptor being worked on: %08x\n",((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_CURDESC/4)]); 
  
  printf("S2MM RXEOF: %08x\n",status_reg & STATUS_RXEOF);  
    printf("S2MM RXSOF: %08x\n",status_reg & STATUS_RXSOF);  
    
  // Check if DMA Channel is Idle
  do{
    status_reg = ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMASR/4)] & DMASR_IDLE;
    usleep(10);
  }while(status_reg != DMASR_IDLE);
  
  printf("S2MM channel is idle\n");

  
  // Currently just checks transmission of first descriptor
  status_reg = ((unsigned int*)bar_ptr)[(desc_base/4) + (STATUS/4)];

  printf("Bytes transferred for first descriptor: %08x\n",status_reg & STATUS_TRANSF);

  if(status_reg & STATUS_CMPLT)
    printf("Descriptor transfer completed successfuly\n");
  else{
    printf("Error: Could not complete descriptor transfer\n");
    return -1;
  } 
  
  // Stop the S2MM channel by setting run/stop bit to 0
    ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] =  ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMACR/4)] & ~DMACR_RS;

  return 0;
}

int waitIOC(pd_device_t *pdev, void *bar_ptr)
{
 unsigned int status_reg_s2mm, status_reg_mm2s;
 
 if( pd_waitForInterrupt(pdev, 0) < 0){
    printf("Error: Could not wait for interrupt\n");
    return -1;
 }
 
   

 status_reg_mm2s = ((unsigned int*)bar_ptr)[DMA_INDEX + (MM2S_DMASR/4)];
 status_reg_s2mm = ((unsigned int*)bar_ptr)[DMA_INDEX + (S2MM_DMASR/4)];

 if(status_reg_mm2s & DMASR_IOC_IRQ)
   printf("Received interrupt for MM2S completion\n");
 if(status_reg_s2mm & DMASR_IOC_IRQ)
   printf("Received interrupt for S2MM completion\n");
 
 if(status_reg_mm2s & DMASR_ERR_IRQ)
   printf("Received interrupt on error for MM2S completion\n");
 if(status_reg_s2mm & DMASR_ERR_IRQ)
   printf("Received interrupt on error for S2MM completion\n");

 return 0;
  
}

int DMAsend(pd_device_t *pdev, void *user_buffer, unsigned int buf_size)
{
  pd_umem_t um;
  void *bar;
  unsigned int tail_desc;
  pd_umem_t *umem_tr;
  unsigned int base_axi2pcie;
  
  int i;
  struct timeval tv1,tv2;

  // Map user buffer into device space
  
  if(pd_mapUserMemory( pdev, user_buffer, buf_size, &um) < 0){
      printf("Error: Could not allocate provided user buffer\n");
      return -1;
  }
  
  // Map the PCI BAR0
  
  bar = pd_mapBAR(pdev,0);
  if (bar == NULL) {
	  printf("Error: Could not map BAR0\n");
	  return -1;
  }
  
  resetBRAM(bar);
  
  // Translate addresses to the AXI bus side
  if( addrTranslation(&um, &umem_tr, &base_axi2pcie) < 0){
     printf("Error: Could not translate addresses for the AXI bus\n");
     return -1;
  }

  printf("Setting address translation\n");
  // Set Address translation in the PCIE Core
  if( setAXI2PCIEbar(base_axi2pcie, bar) < 0){
     printf("Error: Could not configure address translation on the PCIe core\n");
     return -1;
  }
  
  printf("Resetting DMA controller\n");
  // Reset DMA controller
  MM2Sreset(bar);


   printf("Writing SG descriptors to BRAM\n");
  // Setup translated SG descriptors in the BRAM
  if(setupSGDesc(umem_tr,bar,BRAM_BASE,&tail_desc) < 0){
      printf("Error: Could not setup DMA transfer\n");
      return -1;
  }
  
    //dumpBRAM(bar);

  gettimeofday(&tv1,NULL);  
 
  //printf("Starting DMA send\n");  
  if(startDMAsend(bar,BRAM_BASE, tail_desc) < 0){
      printf("Error: Could not start DMA transfer\n");
      return -1;
  }

  //printf("Wait on interrupt\n");
  /*if(waitIOC(pdev,bar)<0){
     printf("Error: Wait on interrupt failed\n");
     return -1;
  }*/
  gettimeofday(&tv2,NULL);

  printf("Time elapsed: %u\n",tv2.tv_usec - tv1.tv_usec);
  
  // Check DMA status and completion
  if(checkSendCompletion(bar,BRAM_BASE) < 0){
     printf("Error: DMA transfer failed\n");
     return -1;
  }
	
   if(pd_unmapBAR(pdev,0,bar)<0){
     printf("Error: Could not unmpap BAR0\n");
     return -1;
   }

   if(pd_unmapUserMemory( &um ) < 0){
      printf("Error: Could not unmap user memory\n");
   }  

   free(umem_tr);
   
  return 0;
}

int DMArecv(pd_device_t *pdev, void *user_buffer, unsigned int buf_size)
{
  pd_umem_t um;
  void *bar;
  unsigned int tail_desc;
  pd_umem_t *umem_tr;
  unsigned int base_axi2pcie;
  
  int i;

  // Map user buffer into device space
  
  if(pd_mapUserMemory( pdev, user_buffer, buf_size, &um) < 0){
      printf("Error: Could not allocate provided user buffer\n");
      return -1;
  }

  
  // Map the PCI BAR0
  
  bar = pd_mapBAR(pdev,0);
  if (bar == NULL) {
	  printf("Error: Could not map BAR0\n");
	  return -1;
  }

  resetBRAM(bar);

  // Translate addresses to the AXI bus side
  if( addrTranslation(&um, &umem_tr, &base_axi2pcie) < 0){
     printf("Error: Could not translate addresses for the AXI bus\n");
     return -1;
  }

  // Set Address translation in the PCIE Core
  if( setAXI2PCIEbar(base_axi2pcie, bar) < 0){
     printf("Error: Could not configure address translation on the PCIe core\n");
     return -1;
  }
  
  // Reset DMA controller
  //DMAreset(bar);


  // Setup translated SG descriptors in the BRAM (on the second half)
  if(setupSGDesc(umem_tr,bar,BRAM_BASE+0x800,&tail_desc) < 0){
      printf("Error: Could not setup DMA transfer\n");
      return -1;
  }
  
  if(startDMArecv(bar,BRAM_BASE+0x800, tail_desc) < 0){
      printf("Error: Could not start DMA transfer\n");
      return -1;
  }
 /* 
  printf("Wait on interrupt\n");
  if(waitIOC(pdev,bar)<0){
     printf("Error: Wait on interrupt failed\n");
     return -1;
  }
  */
  //dumpBRAM(bar);
  
  // Check DMA status and completion
  if(checkRecvCompletion(bar,BRAM_BASE+0x800) < 0){
     printf("Error: DMA transfer failed\n");
     return -1;
  }
	
   if(pd_unmapBAR(pdev,0,bar)<0){
     printf("Error: Could not unmpap BAR0\n");
     return -1;
   }
	
   
  if(pd_syncUserMemory(&um, PD_DIR_FROMDEVICE) <0){
      printf("Error: Could not sync user memory\n");
      return -1;
  }
  
  if(pd_unmapUserMemory( &um ) < 0){
      printf("Error: Could not unmap user memory\n");
  }
   
   free(umem_tr);
   
  return 0;
}


int main() 
{
	int i;
	pd_device_t dev;
	void *mems, *memr;
	unsigned int size = 4096;
	
	printf("VC707 PCIE Test on fpga0\n");
	
		
	// Opening device fpga0
	if(pd_open(0,&dev) != 0){
	    printf("Failed to open file \n");
	    return -1;
	}
	
	printf("Device file opened successfuly\n");
	
	// Create block of 1kB memory
	posix_memalign( (void**)&mems, 16, 1*size );
	
	// Fill memory block
	for(i=0;i<1024;i++)
	  ((unsigned int*)mems)[i] = 5;
	printf("Sent memory block:\n");
	for(i=0;i<1024;i++)
	  printf("%d ",((unsigned int*)mems)[i]);
	printf("\n\n");
	
	// Send data through DMA	
	if( DMAsend(&dev, mems, 4096) < 0){
	printf("DMA send failed\n");
	  
	pd_close( &dev );
	printf("Device file closed successfuly\n");

	free(mems);

	return -1;
	}

	// Create block of 1kB memory
	posix_memalign( (void**)&memr, 16, size );

	// Receive data through DMA
	if( DMArecv(&dev, memr,4096) < 0){
	  printf("DMA recv failed\n");
	  
	pd_close( &dev );
	printf("Device file closed successfuly\n");

	free(mems);
	free(memr);
	  return -1;
	}
	
	printf("\n\n");
	printf("Received memory block:\n");
	for(i=0;i<1024;i++)
	  printf("%d ",((unsigned int*)memr)[i]);

	
	//PCIconfig(&dev);
	
	//testPCImmap(&dev,1,2);
	//testUserMemory(&dev);
	
	pd_close( &dev );
	printf("Device file closed successfuly\n");

	free(mems);
	free(memr);

	return 0;
}