ee478_16_bit_arm_cpu_w_aes_accelerator

Harden memory from memory generator was a part of this project, and they are replaced by behavioral model in this repo.
./cpu/cpu_pipeline_aes.sv is the top level of the project final work.

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
add8		add8
aes		aes
cpu		cpu
func_test		func_test
mem		mem
D_FF.sv		D_FF.sv
README.md		README.md
alu_1.sv		alu_1.sv
alu_16.sv		alu_16.sv
cond_matcher.sv		cond_matcher.sv
controlLogic.sv		controlLogic.sv
controlLogic_pipeline.sv		controlLogic_pipeline.sv
controlLogic_pipeline_aes.sv		controlLogic_pipeline_aes.sv
data_reg_2r1w.sv		data_reg_2r1w.sv
fullAdder.sv		fullAdder.sv
fullAdder_16.sv		fullAdder_16.sv
mux2_1.sv		mux2_1.sv
mux32_16.sv		mux32_16.sv
mux4_1.sv		mux4_1.sv
mux64_16.sv		mux64_16.sv
mux6_3.sv		mux6_3.sv
mux8_1.sv		mux8_1.sv
regfile.txt		regfile.txt
shifter.sv		shifter.sv
signExtend.sv		signExtend.sv

Songchun-Li/ee478_16_bit_arm_cpu_w_aes_accelerator

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ee478_16_bit_arm_cpu_w_aes_accelerator

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