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Fixedpoint wrong generation for Verilog only #110
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Hi,
wire [9:0] _zz_6; is working as an logical shift left which add one bit on the left and fill with zero on the right. (as i wanted) So i tested with Icarus Verilog, are you sure that "'<<<' which are NOT adding any extra bits to LHS" ? http://www-inst.eecs.berkeley.edu/~cs150/fa06/Labs/verilog-ieee.pdf 4.1.12 Shift operators Let's me know your thought :) |
My bad, just leaving comment below for history reference |
Hoo no worries :) |
ok...opening again because vcs2017 is not happy at all but vivado seems ok module bla(
input [7:0] d2_1,
...
);
...
wire [8:0] d2_2;
assign d2_2 = (d2_1 <<< 1); The last assign is not correct(vcs2017 at least) assign d2_2 = ($signed(d2_1) <<< 1); or declare d2_1 as signed then all is ok. |
What happend in VCS in the assign d2_2 = (d2_1 <<< 1); case ? |
Correct and it makes sense, |
Should be fixed by 4f7a1dd |
Fix released in 1.1.3 |
This can be correctly generated for vhdl only
in verilog you use operators '<<<' or '>>>' which are NOT adding any extra bits to LHS
In Vhdl functions pkg_shiftLeft are good way to use
but shifts >> or >>> or <<< or << are common mistake in verilog bit expansion
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