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Hi,
talking about latches (let's say today is Latch day ;) ), even if they are rarely used, they might be useful (for instance in describing clock gating cells).
I would propose to allow the intentional introduction of Latches, using tags, just as we do with combinatorial loops (with the "noCombinatorialLoopCheck" tag)
For instance, introducing a tag called "noLatchCheck" or something similar, we could define latches like follws:
vald=Boolvale=Boolvall=Bool addTag(noLatchCheck)
when (e) {
l := d
}
This would need to be translated in Verilog as:
wire e;
wire d;
reg l;
always @ (e or d)
beginif(e)begin
l <= d;
endend
Let me point out that in Verilog (I don't know about VHDL) latches should be assigned using the non-blocking assignment ("<=") instead of the blocking assignment ("=").
Just a proposal, let me know what you think.
Thanks!
The text was updated successfully, but these errors were encountered:
So until now, the idea was "If you want latches, you have to instanciate them through blackboxes"
But now it could be possible to integrate the feature in reworkDev branch, be before trying it, i would like to release the reworkDev branch into the master one, see if everything is fine, get some feedbacks, and later adding new feature of this order (latches).
Until that time, is the blaboxing way enough ?
Maybe those blackboxes could be integrated into devRework, and be instanciated via a wrapper. Then when the feature is nativly supported it would not need any changes in the user code base.
Hi,
talking about latches (let's say today is Latch day ;) ), even if they are rarely used, they might be useful (for instance in describing clock gating cells).
I would propose to allow the intentional introduction of Latches, using tags, just as we do with combinatorial loops (with the "noCombinatorialLoopCheck" tag)
For instance, introducing a tag called "noLatchCheck" or something similar, we could define latches like follws:
This would need to be translated in Verilog as:
Let me point out that in Verilog (I don't know about VHDL) latches should be assigned using the non-blocking assignment ("<=") instead of the blocking assignment ("=").
Just a proposal, let me know what you think.
Thanks!
The text was updated successfully, but these errors were encountered: