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main_map.map
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main_map.map
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Release 13.2 Map O.61xd (nt)
Xilinx Map Application Log File for Design 'main'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr
off -lc off -power off -o main_map.ncd main.ngd main.pcf
Target Device : xc6slx45
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Dec 10 10:11:12 2012
Mapping design into LUTs...
Running directed packing...
WARNING:Pack:2548 - The register "TFT/tft_vdd_1" has the property IOB=TRUE, but
was not packed into the ILOGIC component.
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 15 secs
Total CPU time at the beginning of Placer: 15 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:6fbbe162) REAL time: 17 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:6fbbe162) REAL time: 18 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:6fbbe162) REAL time: 18 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:88f73fb3) REAL time: 32 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:88f73fb3) REAL time: 32 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:88f73fb3) REAL time: 32 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:88f73fb3) REAL time: 32 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:88f73fb3) REAL time: 32 secs
Phase 9.8 Global Placement
..............................................................................................
.....................................
Phase 9.8 Global Placement (Checksum:b4749f12) REAL time: 40 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:b4749f12) REAL time: 40 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:da62ea72) REAL time: 2 mins 12 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:da62ea72) REAL time: 2 mins 12 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:da62ea72) REAL time: 2 mins 13 secs
Total REAL time to Placer completion: 2 mins 18 secs
Total CPU time to Placer completion: 2 mins 16 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <JB<0>_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <JB<1>_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <JB<2>_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <JB<3>_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <JB<4>_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <JB<5>_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <button_center_IBUF> is incomplete. The signal does not drive any load pins in
the design.
WARNING:PhysDesignRules:367 - The signal <button_up_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <touch_busy_IBUF> is incomplete. The signal does not drive any load pins in the
design.
WARNING:PhysDesignRules:367 - The signal <button_right_IBUF> is incomplete. The signal does not drive any load pins in
the design.
WARNING:PhysDesignRules:367 - The signal <button_left_IBUF> is incomplete. The signal does not drive any load pins in
the design.
WARNING:PhysDesignRules:367 - The signal <button_down_IBUF> is incomplete. The signal does not drive any load pins in
the design.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 13
Slice Logic Utilization:
Number of Slice Registers: 671 out of 54,576 1%
Number used as Flip Flops: 671
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 3,413 out of 27,288 12%
Number used as logic: 3,399 out of 27,288 12%
Number using O6 output only: 2,059
Number using O5 output only: 87
Number using O5 and O6: 1,253
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 14
Number with same-slice register load: 5
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,208 out of 6,822 17%
Number of LUT Flip Flop pairs used: 3,438
Number with an unused Flip Flop: 2,790 out of 3,438 81%
Number with an unused LUT: 25 out of 3,438 1%
Number of fully used LUT-FF pairs: 623 out of 3,438 18%
Number of unique control sets: 38
Number of slice register sites lost
to control set restrictions: 145 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 65 out of 218 29%
Number of LOCed IOBs: 65 out of 65 100%
IOB Flip Flops: 3
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 1 out of 376 1%
Number used as ILOGIC2s: 1
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 2 out of 376 1%
Number used as OLOGIC2s: 2
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.97
Peak Memory Usage: 288 MB
Total REAL time to MAP completion: 2 mins 21 secs
Total CPU time to MAP completion (all processors): 2 mins 19 secs
Mapping completed.
See MAP report file "main_map.mrp" for details.