LineBuffers are two dimensional, on-chip scratchpads with a fixed size. LineBuffers act as a FIFO on input, supporting only queued writes, but support addressed reading like SRAMs. For writes, the current row buffer and column is maintained using an internal counter. This counter resets every time the controller containing the enqueue completes execution.
The contents of LineBuffers are persistent across loop iterations, even when they are declared in an inner scope. Up to 5-dimensional LineBuffers are currently supported.
Static methods
| object LineBuffer | |
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def apply[T::doc:`Type <../../typeclasses/type>`::doc:`Bits <../../typeclasses/bits>`](rows: :doc:`Index <../../common/fixpt>`, cols: :doc:`Index <../../common/fixpt>`): :doc:`LineBuffer <linebuffer>`[T]
Allocates a LineBuffer with given rows and cols.
The contents of this LineBuffer are initially undefined.
rows and cols must be statically determinable integers.
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def strided[T::doc:`Type <../../typeclasses/type>`::doc:`Bits <../../typeclasses/bits>`](rows: :doc:`Index <../../common/fixpt>`, cols: :doc:`Index <../../common/fixpt>`, stride: :doc:`Index <../../common/fixpt>`): :doc:`LineBuffer <linebuffer>`[T]
Allocates a LineBuffer with given number of rows and cols, and with given stride.
The contents of this LineBuffer are initially undefined.
rows, cols, and stride must be statically determinable integers.
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Infix methods
| class LineBuffer[T] | |
|---|---|
def apply(row: :doc:`Index <../../common/fixpt>`, col: :doc:`Index <../../common/fixpt>`): T
Creates a load port to this LineBuffer at the given row and col.
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def apply(row: :doc:`Index <../../common/fixpt>`, cols: :doc:`Range <../../common/range>`)(implicit ctx: SrcCtx): :doc:`Vector <../../common/vector>`[T]
Creates a vectorized load port to this LineBuffer at the given row and cols.
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def apply(rows: :doc:`Range <../../common/range>`, col: :doc:`Index <../../common/fixpt>`)(implicit ctx: SrcCtx): :doc:`Vector <../../common/vector>`[T]
Creates a vectorized load port to this LineBuffer at the given rows and col.
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def enq(data: T): :doc:`Unit <../../common/unit>`
Creates an enqueue (write) port of data to this LineBuffer.
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def enq(data: T, en: :doc:`Bit <../../common/bit>`): :doc:`Unit <../../common/unit>`
Creates an enqueue (write) port of data to this LineBuffer, enabled by en.
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def load(dram: :doc:`DRAMDenseTile1 <../offchip/tile>`[T])(implicit ctx: SrcCtx): :doc:`Unit <../../common/unit>`
Creates a dense transfer from the given region of DRAM to this on-chip memory.
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