7.md

CS 150: Digital Design & Computer Architecture

September 11, 2012

Changed office hours this week. CLBs, SAR, K-maps.

Last time: we went from transistors to inverters with enable to D-flipflops to a shift register with some inputs and outputs, and, from there to the idea that once you have that shift register, then you can hook that up with an n-input mux and make an arbitrary function of n variables.

This gives me configurable logic and configurable interconnects, and naturally I take the shift out of one and into another, and I've got an FPGA.

The LUT is the basic building block: I get four of those per slice, and some other stuff: includes fast ripple carry logic for adders, the ability to take two 6s and put them together to form a 7-LUT. So: pretty flexible, fair amount of logic, and that's a slice. One CLB is equal to two slices.

And I've got, what is that, 8640 CLBs per chip. Also: DSP48 blocks. 64 of these, and each one is a little 48-bit configurable ALU. So that gives you something like 70000 (6-LUTs + D-ff). So that's what you've got, what we work with.

Now, let's talk about a successive approximation register analog to digital converter. A very popular device. Link to a chip that implemented the digital piece of this thirty years ago. Why are we looking at this? It's nice; it's an example of a "mixed-signal" (i.e. analog mixed with digital in the same block, where you have a good amount of both) system.

It turns out that analog designers need to be good digital designers these days. I was doing some consulting for a company recently. They had brilliant analog designers, but they had to do some digital blocks on their chips.

"Real world" interfaces. Has some number of output bits that go into the DAC; the DAC's output is simply "linear". You trust the analog designer to give you this piece, and the digital comparator sample and hold circuit, with the sample input, and here's your analog input voltage. So real quick we'll look at what's in those blocks (even though this isn't 150 material). S/H: simplest example is just a transistor. Maybe it's a butterfly gate; typically, there's some storage capacitor on the outside so that if you've got your input voltage; when it goes low, that is held on there.

Maybe there's some buffer amplifier (little CMOS opamp so it can drive nice loads); capacitive input, so signal will stay there for a long time. Not 150 material.

The DAC, a simple way of making this is to generate a reference voltage (diode-connected PMOS with voltage division, say). which you mirror, tied together with a switch, and all of these share the same gate. Comparator's a little more subtle. Maybe when we talk about SRAMs and DRAMs.

Anyway. So. Now we have the ability to generate an analog voltage under digital control. We sample that input and are going to use that signal. This tells us whether the output of the DAC is too big. That together is called a SAR.

So what does that thing do? There's a very simple (dumb) SAR: a counter. From reset in time, its digital output increases linearly; at some point it crosses the analog $V_{in}$, and at that point, you stop. But: that's not such a great thing to do: between 1 and 1024 cycles to get the result. The better way is to do a binary search. Fun to do with dictionaries and kids. Also works here. FSM: go bit-by-bit, starting with most significant bit.

Better solution (instead of using oversized tree -- better in the sense of less logic required): use a shift register (and compute all bits sequentially). Or counter going into a decoder; sixteen outputs of which I only need 10.

Next piece: another common challenge and where a lot of mistakes get made: analog stuff does not simulate as well. While you're developing and debugging, you have to come up with some way of simulating.

Good news: you can often go in and fix things like that. Sort of an aside (although it sometimes shows up in my exams), once you put these transistors down, and then you've got all these layers of metal on top. Turns out that you can actually put this thing in a scanning electron microscope and use undedicated logic and go in with a FIB (focused ion beam) and fix problems. "Metal spin".

Back to chapter two: basic gates again. de Morgan's law: $\bar{AB} = \bar{A} + \bar{B}$: $\bar{\prod{A_i}} = \sum \bar{A_i}$. Similarly, $\bar{\sum{A_i}} = \prod \bar{A_i}$. Suppose you have a two-level NAND/NAND gate: that becomes a sum of products (SoP). Similarly, NOR/NOR is equivalent to a product of sums (PoS).

Now, if I do NOR/NOR/INV, this is a sum of products, but the inputs are inverted. This is an important one. This particular one is useful because of the way you can design logic. The way we used to design logic a few decades ago (and the way we might go back in the future) was with big long strings of NOR gates.

So if I go back to our picture of a common source amplifier (erm, inverter), and we stick a bunch of other transistors in parallel, then we have a NOR gate. Remember: MOS devices have parasitic capacitance.

Consider another configuration. Suppose we invert our initial input and connect to both of these a circled wire, which can be any of the following: fuse / anti-fuse, mask-programmable (when you make the mask, decision to add a contact), transistor with flipflop (part of shift register, e.g.), an extra gate (double-gate transistors).

So now if I chain a bunch more of these together (all NOR'd together, then I can program many functions. In particular, it could just be an inverter.

I can put a bunch of these together, and I can combine the function outputs with another set of NORs, invert it all at the end, and I end up with NOR/NOR/INV.

These guys are called PLAs (programmable logic arrays), and you can still buy them, and they're still useful. Not uncommon to have a couple of flipflops on them. Will have a homework assignment where you use a 30 cent PLA and design something. Quick and dirty way of getting something for cheap.

Not done anymore because slow (huge capacitances), but may come back because of carbon nanotubes. Javey managed to make a nanotube transistor with a source, drain, gate, and he got transport, highest current density per square micron cross-section ever, and showed physics all worked, and this thing is 1nm around. What Prof. Ali Javey's doing now is working with nanowires and showing that you can grow these things on a roller and roll them onto a surface (like a plastic surface), and putting down layers of nanowires in alternating directions.

You can imagine (we're a ways away from this) where you get a transistor at each of these locations, and you've got some CMOS on this side generating signals, and CMOS on the output taking the output (made with big fat gigantic 14nm transistors), and you can put $10^5$ transistors per square micron (not pushing it, since density can get up to $10^6$). End of road for CMOS doesn't mean you ditch CMOS. Imagine making this into a jungle gym; then you're talking about $10^8$ carbon nanotubes per cubic micron, etc. The fact that we can make these long thin transistors on their lengths means that this might come back into fashion.