[code-structure] Add all STM32 Core-IDs to the codebase for MCU identification

[Nightwalker-87]

We have Core-IDs defined in /include/stlink/stm32.h which are used to detect chips correctly.
However this is implemented differently for the various STM32 product lines which is not very clever nor follows any visible logic structure. The current situation is as follows:

/* STM32 Cortex-M core ids (CPUTAPID) */

#define STM32_CORE_ID_M0_SWD 0x0bb11477
// (RM0091 Section 32.5.3) F0 SW-DP
// (RM0444 Section 40.5.3) G0 SW-DP

#define STM32_CORE_ID_M0P_SWD 0x0bc11477
// (RM0385 Section 27.5.3) L0 SW-DP

#define STM32_CORE_ID_M3_r1p1_SWD 0x1ba01477
// (RM0008 Section 31.8.3) F1 SW-DP
#define STM32_CORE_ID_M3_r1p1_JTAG 0x3ba00477
// (RM0008 Section 31.6.3) F1 JTAG

#define STM32_CORE_ID_M3_r2p0_SWD 0x2ba01477
// (RM0033 Section 32.8.3) F2 SW-DP
// (RM0038 Section 30.8.3) L1 SW-DP
#define STM32_CORE_ID_M3_r2p0_JTAG 0x0ba00477
// (RM0033 Section 32.6.3) F2 JTAG
// (RM0038 Section 30.6.2) L1 JTAG

#define STM32_CORE_ID_M4_r0p1_SWD 0x1ba01477
// (RM0316 Section 33.8.3) F3 SW-DP
// (RM0351 Section 48.8.3) L4 SW-DP
// (RM0432 Section 57.8.3) L4+ SW-DP
#define STM32_CORE_ID_M4_r0p1_JTAG 0x4ba00477
// (RM0316 Section 33.6.3) F3 JTAG
// (RM0351 Section 48.6.3) L4 JTAG
// (RM0432 Section 57.6.3) L4+ JTAG

#define STM32_CORE_ID_M4F_r0p1_SWD 0x2ba01477
// (RM0090 Section 38.8.3) F4 SW-DP
// (RM0090 Section 47.8.3) G4 SW-DP
#define STM32_CORE_ID_M4F_r0p1_JTAG 0x4ba00477
// (RM0090 Section 38.6.3) F4 JTAG
// (RM0090 Section 47.6.3) G4 JTAG

#define STM32_CORE_ID_M7F_SWD 0x5ba02477
// (RM0385 Section 40.8.3) F7 SW-DP
#define STM32_CORE_ID_M7F_JTAG 0x5ba00477
// (RM0385 Section 40.6.3) F7 JTAG

#define STM32_CORE_ID_M7F_H7_SWD 0x6ba02477
// (RM0433 Section 60.4.1) H7 SW-DP
#define STM32_CORE_ID_M7F_H7_JTAG 0x6ba00477
// (RM0433 Section 60.4.1) H7 JTAG

#define STM32_CORE_ID_M33_SWD 0x0be02477
// (RM0438 Section 52.2.10) L5 SW-DP
// (RM0456 Section 65.3.3) U5 SW-DP
#define STM32_CORE_ID_M33_JTAGD 0x0be01477
// (RM0438 Section 52.2.10) L5 JTAG-DP
// (RM0456 Section 65.3.3) U5 JTAG-DP
#define STM32_CORE_ID_M33_JTAG 0x0ba04477
// (RM0438 Section 52.2.8) L5 JTAG
// (RM0456 Section 56.3.1) U5 JTAG

In reference to #756 and #761 this seems not to have been implemented well over time and should be commonly addressed.

[grevaillot]

hmm, while evaluating codebase to support H7/L5, i extracted a bit of an old H7 support patch and reworked it to do somethink like that

it's here : grevaillot@5b8ade2

i need to have a look at chips RM instead of defaulting to some default address for identification, but, as it, it works for the few devices i have in hand.

[Nightwalker-87]

I'd propose to identify every MCUs via the following hierarchical workflow:

1. Read Core-ID
2. Read Chip-ID (by use of a unified macro naming scheme)
3. Read specific parameters taken from /src/chip-id.c

[houzhuhouzhu]

how to deal with ?

[Nightwalker-87]

Yeah indeed, I've been waiting for some feedback here as well...

[Ant-ON]

@houzhuhouzhu
@Nightwalker-87
A similar implementation was done in PR #1120. Now it is used in release version. I have not heard any problem on the work yet...

[houzhuhouzhu]

oh look it，maybe,I can rewrite it

[Nightwalker-87]

@Ant-ON Yes, but as far as I noticed there are even more chip IDs that are currently not used for detection.