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mod.rs
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/*!Peripheral access API for STM32G491XX microcontrollers (generated using svd2rust v0.33.4 (5b6615e 2024-06-16))
You can find an overview of the generated API [here].
API features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api
[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
[repository]: https://github.com/rust-embedded/svd2rust*/
use core::marker::PhantomData;
use core::ops::Deref;
///Number available in the NVIC for configuring priority
pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
fn WWDG();
fn PVD_PVM();
fn RTC_TAMP_CSS_LSE();
fn RTC_WKUP();
fn FLASH();
fn RCC();
fn EXTI0();
fn EXTI1();
fn EXTI2();
fn EXTI3();
fn EXTI4();
fn DMA1_CH1();
fn DMA1_CH2();
fn DMA1_CH3();
fn DMA1_CH4();
fn DMA1_CH5();
fn DMA1_CH6();
fn ADC1_2();
fn USB_HP();
fn USB_LP();
fn FDCAN1_INTR1_IT();
fn FDCAN1_INTR0_IT();
fn EXTI9_5();
fn TIM1_BRK_TIM15();
fn TIM1_UP_TIM16();
fn TIM1_TRG_COM();
fn TIM1_CC();
fn TIM2();
fn TIM3();
fn TIM4();
fn I2C1_EV();
fn I2C1_ER();
fn I2C2_EV();
fn I2C2_ER();
fn SPI1();
fn SPI2();
fn USART1();
fn USART2();
fn USART3();
fn EXTI15_10();
fn RTC_ALARM();
fn USBWAKE_UP();
fn TIM8_BRK();
fn TIM8_UP();
fn TIM8_TRG_COM();
fn TIM8_CC();
fn ADC3();
fn LPTIM1();
fn SPI3();
fn UART4();
fn UART5();
fn TIM6_DACUNDER();
fn TIM7();
fn DMA2_CH1();
fn DMA2_CH2();
fn DMA2_CH3();
fn DMA2_CH4();
fn DMA2_CH5();
fn UCPD1();
fn COMP1_2_3();
fn COMP4();
fn CRS();
fn SAI();
fn FPU();
fn FDCAN2_INTR0();
fn FDCAN2_INTR1();
fn RNG();
fn LPUART();
fn I2C3_EV();
fn I2C3_ER();
fn DMAMUX_OVR();
fn DMA2_CH6();
fn CORDIC();
fn FMAC();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 102] = [
Vector { _handler: WWDG },
Vector { _handler: PVD_PVM },
Vector {
_handler: RTC_TAMP_CSS_LSE,
},
Vector { _handler: RTC_WKUP },
Vector { _handler: FLASH },
Vector { _handler: RCC },
Vector { _handler: EXTI0 },
Vector { _handler: EXTI1 },
Vector { _handler: EXTI2 },
Vector { _handler: EXTI3 },
Vector { _handler: EXTI4 },
Vector { _handler: DMA1_CH1 },
Vector { _handler: DMA1_CH2 },
Vector { _handler: DMA1_CH3 },
Vector { _handler: DMA1_CH4 },
Vector { _handler: DMA1_CH5 },
Vector { _handler: DMA1_CH6 },
Vector { _reserved: 0 },
Vector { _handler: ADC1_2 },
Vector { _handler: USB_HP },
Vector { _handler: USB_LP },
Vector {
_handler: FDCAN1_INTR1_IT,
},
Vector {
_handler: FDCAN1_INTR0_IT,
},
Vector { _handler: EXTI9_5 },
Vector {
_handler: TIM1_BRK_TIM15,
},
Vector {
_handler: TIM1_UP_TIM16,
},
Vector {
_handler: TIM1_TRG_COM,
},
Vector { _handler: TIM1_CC },
Vector { _handler: TIM2 },
Vector { _handler: TIM3 },
Vector { _handler: TIM4 },
Vector { _handler: I2C1_EV },
Vector { _handler: I2C1_ER },
Vector { _handler: I2C2_EV },
Vector { _handler: I2C2_ER },
Vector { _handler: SPI1 },
Vector { _handler: SPI2 },
Vector { _handler: USART1 },
Vector { _handler: USART2 },
Vector { _handler: USART3 },
Vector {
_handler: EXTI15_10,
},
Vector {
_handler: RTC_ALARM,
},
Vector {
_handler: USBWAKE_UP,
},
Vector { _handler: TIM8_BRK },
Vector { _handler: TIM8_UP },
Vector {
_handler: TIM8_TRG_COM,
},
Vector { _handler: TIM8_CC },
Vector { _handler: ADC3 },
Vector { _reserved: 0 },
Vector { _handler: LPTIM1 },
Vector { _reserved: 0 },
Vector { _handler: SPI3 },
Vector { _handler: UART4 },
Vector { _handler: UART5 },
Vector {
_handler: TIM6_DACUNDER,
},
Vector { _handler: TIM7 },
Vector { _handler: DMA2_CH1 },
Vector { _handler: DMA2_CH2 },
Vector { _handler: DMA2_CH3 },
Vector { _handler: DMA2_CH4 },
Vector { _handler: DMA2_CH5 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: UCPD1 },
Vector {
_handler: COMP1_2_3,
},
Vector { _handler: COMP4 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: CRS },
Vector { _handler: SAI },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: FPU },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector {
_handler: FDCAN2_INTR0,
},
Vector {
_handler: FDCAN2_INTR1,
},
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: RNG },
Vector { _handler: LPUART },
Vector { _handler: I2C3_EV },
Vector { _handler: I2C3_ER },
Vector {
_handler: DMAMUX_OVR,
},
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: DMA2_CH6 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: CORDIC },
Vector { _handler: FMAC },
];
///Enumeration of all the interrupts.
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
///0 - Window Watchdog interrupt
WWDG = 0,
///1 - PVD through EXTI line detection
PVD_PVM = 1,
///2 - RTC_TAMP_CSS_LSE
RTC_TAMP_CSS_LSE = 2,
///3 - RTC Wakeup timer
RTC_WKUP = 3,
///4 - FLASH
FLASH = 4,
///5 - RCC
RCC = 5,
///6 - EXTI Line0 interrupt
EXTI0 = 6,
///7 - EXTI Line1 interrupt
EXTI1 = 7,
///8 - EXTI Line2 interrupt
EXTI2 = 8,
///9 - EXTI Line3 interrupt
EXTI3 = 9,
///10 - EXTI Line4 interrupt
EXTI4 = 10,
///11 - DMA1 channel 1 interrupt
DMA1_CH1 = 11,
///12 - DMA1 channel 2 interrupt
DMA1_CH2 = 12,
///13 - DMA1 channel 3 interrupt
DMA1_CH3 = 13,
///14 - DMA1 channel 4 interrupt
DMA1_CH4 = 14,
///15 - DMA1 channel 5 interrupt
DMA1_CH5 = 15,
///16 - DMA1 channel 6 interrupt
DMA1_CH6 = 16,
///18 - ADC1 and ADC2 global interrupt
ADC1_2 = 18,
///19 - USB_HP
USB_HP = 19,
///20 - USB_LP
USB_LP = 20,
///21 - fdcan1_intr1_it
FDCAN1_INTR1_IT = 21,
///22 - fdcan1_intr0_it
FDCAN1_INTR0_IT = 22,
///23 - EXTI9_5
EXTI9_5 = 23,
///24 - TIM1_BRK_TIM15
TIM1_BRK_TIM15 = 24,
///25 - TIM1_UP_TIM16
TIM1_UP_TIM16 = 25,
///26 - TIM1_TRG_COM/
TIM1_TRG_COM = 26,
///27 - TIM1 capture compare interrupt
TIM1_CC = 27,
///28 - TIM2
TIM2 = 28,
///29 - TIM3
TIM3 = 29,
///30 - TIM4
TIM4 = 30,
///31 - I2C1_EV
I2C1_EV = 31,
///32 - I2C1_ER
I2C1_ER = 32,
///33 - I2C2_EV
I2C2_EV = 33,
///34 - I2C2_ER
I2C2_ER = 34,
///35 - SPI1
SPI1 = 35,
///36 - SPI2
SPI2 = 36,
///37 - USART1
USART1 = 37,
///38 - USART2
USART2 = 38,
///39 - USART3
USART3 = 39,
///40 - EXTI15_10
EXTI15_10 = 40,
///41 - RTC_ALARM
RTC_ALARM = 41,
///42 - USBWakeUP
USBWAKE_UP = 42,
///43 - TIM8_BRK
TIM8_BRK = 43,
///44 - TIM8_UP
TIM8_UP = 44,
///45 - TIM8_TRG_COM
TIM8_TRG_COM = 45,
///46 - TIM8_CC
TIM8_CC = 46,
///47 - ADC3
ADC3 = 47,
///49 - LPTIM1
LPTIM1 = 49,
///51 - SPI3
SPI3 = 51,
///52 - UART4
UART4 = 52,
///53 - UART5
UART5 = 53,
///54 - TIM6_DACUNDER
TIM6_DACUNDER = 54,
///55 - TIM7
TIM7 = 55,
///56 - DMA2_CH1
DMA2_CH1 = 56,
///57 - DMA2_CH2
DMA2_CH2 = 57,
///58 - DMA2_CH3
DMA2_CH3 = 58,
///59 - DMA2_CH4
DMA2_CH4 = 59,
///60 - DMA2_CH5
DMA2_CH5 = 60,
///63 - UCPD1
UCPD1 = 63,
///64 - COMP1_2_3
COMP1_2_3 = 64,
///65 - COMP4_5_6
COMP4 = 65,
///75 - CRS
CRS = 75,
///76 - SAI
SAI = 76,
///81 - Floating point unit interrupt
FPU = 81,
///86 - FDCAN2_intr0
FDCAN2_INTR0 = 86,
///87 - FDCAN2_intr1
FDCAN2_INTR1 = 87,
///90 - RNG
RNG = 90,
///91 - LPUART
LPUART = 91,
///92 - I2C3_EV
I2C3_EV = 92,
///93 - I2C3_ER
I2C3_ER = 93,
///94 - DMAMUX_OVR
DMAMUX_OVR = 94,
///97 - DMA2_CH6
DMA2_CH6 = 97,
///100 - Cordic
CORDIC = 100,
///101 - FMAC
FMAC = 101,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
self as u16
}
}
///Cyclic redundancy check calculation unit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#CRC)
pub struct CRC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CRC {}
impl CRC {
///Pointer to the register block
pub const PTR: *const crc::RegisterBlock = 0x4002_3000 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const crc::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for CRC {
type Target = crc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for CRC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRC").finish()
}
}
///Cyclic redundancy check calculation unit
pub mod crc;
///WinWATCHDOG
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#IWDG)
pub struct IWDG {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for IWDG {}
impl IWDG {
///Pointer to the register block
pub const PTR: *const iwdg::RegisterBlock = 0x4000_3000 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const iwdg::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for IWDG {
type Target = iwdg::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for IWDG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IWDG").finish()
}
}
///WinWATCHDOG
pub mod iwdg;
///System window watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#WWDG)
pub struct WWDG {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for WWDG {}
impl WWDG {
///Pointer to the register block
pub const PTR: *const wwdg::RegisterBlock = 0x4000_2c00 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const wwdg::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for WWDG {
type Target = wwdg::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for WWDG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WWDG").finish()
}
}
///System window watchdog
pub mod wwdg;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#I2C1)
pub struct I2C1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C1 {}
impl I2C1 {
///Pointer to the register block
pub const PTR: *const i2c1::RegisterBlock = 0x4000_5400 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const i2c1::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for I2C1 {
type Target = i2c1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2C1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C1").finish()
}
}
///Inter-integrated circuit
pub mod i2c1;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#I2C1)
pub struct I2C2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C2 {}
impl I2C2 {
///Pointer to the register block
pub const PTR: *const i2c1::RegisterBlock = 0x4000_5800 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const i2c1::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for I2C2 {
type Target = i2c1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2C2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C2").finish()
}
}
///Inter-integrated circuit
pub use self::i2c1 as i2c2;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#I2C1)
pub struct I2C3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C3 {}
impl I2C3 {
///Pointer to the register block
pub const PTR: *const i2c1::RegisterBlock = 0x4000_7800 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const i2c1::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for I2C3 {
type Target = i2c1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2C3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C3").finish()
}
}
///Inter-integrated circuit
pub use self::i2c1 as i2c3;
///Flash
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#FLASH)
pub struct FLASH {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for FLASH {}
impl FLASH {
///Pointer to the register block
pub const PTR: *const flash::RegisterBlock = 0x4002_2000 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const flash::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for FLASH {
type Target = flash::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for FLASH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH").finish()
}
}
///Flash
pub mod flash;
///Debug support
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#DBGMCU)
pub struct DBGMCU {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DBGMCU {}
impl DBGMCU {
///Pointer to the register block
pub const PTR: *const dbgmcu::RegisterBlock = 0xe004_2000 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const dbgmcu::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for DBGMCU {
type Target = dbgmcu::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DBGMCU {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DBGMCU").finish()
}
}
///Debug support
pub mod dbgmcu;
///Reset and clock control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#RCC)
pub struct RCC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for RCC {}
impl RCC {
///Pointer to the register block
pub const PTR: *const rcc::RegisterBlock = 0x4002_1000 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const rcc::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for RCC {
type Target = rcc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for RCC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RCC").finish()
}
}
///Reset and clock control
pub mod rcc;
///Power control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#PWR)
pub struct PWR {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for PWR {}
impl PWR {
///Pointer to the register block
pub const PTR: *const pwr::RegisterBlock = 0x4000_7000 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const pwr::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for PWR {
type Target = pwr::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for PWR {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PWR").finish()
}
}
///Power control
pub mod pwr;
///Random number generator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#RNG)
pub struct RNG {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for RNG {}
impl RNG {
///Pointer to the register block
pub const PTR: *const rng::RegisterBlock = 0x5006_0800 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const rng::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for RNG {
type Target = rng::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for RNG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RNG").finish()
}
}
///Random number generator
pub mod rng;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#GPIOA)
pub struct GPIOA {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOA {}
impl GPIOA {
///Pointer to the register block
pub const PTR: *const gpioa::RegisterBlock = 0x4800_0000 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate
/// access between multiple new instances.
///
/// Additionally, other software such as HALs may rely on only one
/// peripheral instance existing to ensure memory safety; ensure
/// no stolen instances are passed to such software.
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for GPIOA {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOA").finish()
}
}
///General-purpose I/Os
pub mod gpioa;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G491xx.html#GPIOB)
pub struct GPIOB {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOB {}
impl GPIOB {
///Pointer to the register block
pub const PTR: *const gpiob::RegisterBlock = 0x4800_0400 as *const _;
///Return the pointer to the register block
#[inline(always)]
pub const fn ptr() -> *const gpiob::RegisterBlock {
Self::PTR
}
/// Steal an instance of this peripheral
///
/// # Safety
///
/// Ensure that the new instance of the peripheral cannot be used in a way
/// that may race with any existing instances, for example by only
/// accessing read-only or write-only registers, or by consuming the
/// original peripheral and using critical sections to coordinate