Add clock HSE bypass

[David-OConnor]

If you use a MEMs oscillator etc, you can bypass the oscillator outputs and use them as GPIOs.

Eg does this:

rcc.cr.modify(|_, w| w.hsebyp().bit(true));

With this API:

rcc.set_hse_bypass(true);

Present workaround to deal with private or missing registers in rcc.rs:

unsafe { (*pac::RCC::ptr()).cr.modify(|_, w| w.hsebyp().bit(true)) }

Or maybe you add it to the rcc.cfgr chaining pattern:

    let clocks = rcc
        .cfgr
        .use_hse(8.mhz()) // Use the high-speed external oscillator
        // .hsclk(8.mhz())  // Sets a frequency for the AHB bus
        .pclk1(24.mhz()) // Sets a frequency for the APB1 bus
        // .pclk2(24.mhz ())  // Sets a frequency for the APB2 bus
        .sysclk(48.mhz()) // Sets the system (core) frequency
        // 16-72 Mhz valid range for for PLL. How do we set that?
        .hse_bypass()
        .freeze(&mut flash.acr);

Currently have to use raw pointers due to bdcr being crate-level private, and cr not being exposed at all. I'm on too many forks right now to make this a PR until the timer and DAC ones are closed. Note that in this RTC PR, we skipped some features to avoid CR being exposed. This use case is a second vote for exposing CR on a pub(crate) level as we did bdcr in there.

LSE bypass works in a similar way, and is already handled in the rtc module.