cayde

cayde is a RV32I processor written in SystemVerilog. It is a single-cycle implementation.

Features

• It can run RV32I instructions.
• Other extensions and instructions can be added in the package.

Feature Suggestion

• Improve the core.
• Add M extensions.
• Verify the core.
• Add a pipelined version.
• Add hazard detection.

Instructions to synthesize the core.

You can use any synthesis tool to run this code. I have used Yosys and sv2v here.

Instructions to simulate/verify the core.

W.I.P