CDC issue ?

[xinx]

module scr1_tapc_synchronizer:

Unlike other inputs of domain sysCLK the input 'tapc2tapcsync_ch_tdo_i' (in the version which I work on currently: 'dmi_ch_tdo_core') is not two-staged synchronized to the output tapcsync2core_ch_tdo_o (formerly 'dmi_ch_tdo'). What is the rationale? STA complains about this path in my environment.

Thank you for help and clarification!

[dp-sc]

Hi Xinx

In accordance with JTAG conventions the output signal(TDO) have to be driven at the falling edge of TCK. So, the two stage synchronizer(with TCK destination clock) couldn’t be applied here.
There is a clock ration requirements(1:12) between TCK and system clock. It is guarantee that the signal on TDO will be stable when falling edge is coming.

Syntacore