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The purpose of this group is to enable collaboration and open discussions about:

  1. High Performance Compilers and Optimization techniques that can be applied to TensorFlow graphs.
  2. Code generation

Our overarching goal is to create common intermediate representation (IR) that reduces the cost to bring up new hardware, and improve usability for existing TensorFlow users.


Anyone involved in or interested in high performance compilers and their applications to TensorFlow graphs are welcome to join the group. To participate, request an invitation to join the mailing list. Archives of the mailing list will be publicly accessible.



We plan to start by focusing on the Graph Compiler. As such, we’ll have a 45 min meeting every week. In the near future, we also plan on adding another 45 min slot focussed on Code Generation. Everyone on the mailing list will be invited. We will publish a document for interested members to add topics. The main goals of these meetings will include, but not restricted to:

  1. Design discussions and reviews of upcoming changes.
  2. Roadmap discussions.
  3. Discussions around platform support.
  4. Important issues & bugs.


  • Project lead: Tatiana Shpeisman @tatianashp - shpeisman at google
  • Project manager: Pankaj Kanwar @pkanwar23 - pkanwar at google
  • For administrative questions, contact Edd Wilder-James @ewilderj - ewj at google

Code of Conduct

As with all forums and spaces related to TensorFlow, SIG MLIR is subject to the TensorFlow Code of Conduct.