🍡πŸ–₯ A simple 12 bit RISC CPU architecture made in Logisim + an assembler for it
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TSYS Instructions.txt Initial commit Sep 29, 2018
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readme.md

Something I made over a few nights.

Requires Logisim-Xtended

ROM is 12 bits per word, the first 4 bits being the opcode, last 8 being operand.

add   15

assembles to:
1     0f

resulting in 10f word. 

Use TSYS Instructions.txt as a reference to write the hex codes directly.

To use the simple ASM, build TSYSasm.cr with the Crystal compiler and run with two arguments, the file of the assembly code, and the name of the output file; e.g.

./TSYSasm test.tasm output

You can then load this into the ROM module in Logisim and run it by enabling the clock; ctrl+k