Bad elaboration order

[rroohhh]

Hi,
I am trying to use this with a bigger project targeting the Xilinx Zynq 7020 FPGA.

I am using this script: https://paste.niemo.de/ubehahuwup.sh to try and synthesize the design. It produces the following output: https://paste.niemo.de/raw/lazolamaxo

(The unisim.vhd and unimacro.vhd come from a Vivado installation, they are Vivado/2018.2/data/vhdl/src/unisim/unisim_retarget_VCOMP.vhd and Vivado/2018.2/data/vhdl/src/unimacro/unimacro/unimacro_VCOMP.vhd)

It fails at the yosys step with

error: synth: bad elaboration order of objects

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 1.0-dev (v0.37.0-14-g3a134f43) [Dunoon edition]
Compiled with unknown compiler version
Target: x86_64-linux-gnu
/src/
Command line:

Exception TYPES.INTERNAL_ERROR raised
Exception information:
raised TYPES.INTERNAL_ERROR : synth-context.adb:222
******************************************************************
ERROR: vhdl import failed.

This is of course not a lot of information to work with, but due to the size of the project, I am not sure how do debug / reduce this error further.

Do you have any pointers for me on how to debug this further or reduce the project to something workable?

[tgingold]

I suppose this is due to the use of generic packages. This vhdl-08 feature is not yet supported by synth.

[cajt]

I get the identical error message for a different design.
It uses VHDL-93, so no generic packages.
But it has similar (maybe the same) warnings about unknown pragmas from "src/synopsys/std_logic_arith.vhdl".

Shall I try to build a minimal example, and open an new issue?

[tgingold]

Yes, if you have a vhdl-93 reproducer, please post it. No need to create a new issue. It doesn't need to be minimal, but it is much better when it is stand-alone. The warnings in std_logic_arith could be ignored.

[cajt]

Here is the source: https://github.com/cajt/ghdlsynth-testcase-loa
and its output: https://raw.githubusercontent.com/cajt/ghdlsynth-testcase-loa/master/setup1/log/output.log

[tgingold]

I can reproduce the crash.

[tgingold]

The bad elaboration error is now fixed.

But there are some unimplemented operations that I have to fix.

[tgingold]

ghdl now detects a latch in uart_rx.

[cajt]

Thank you.
I'm trying to reproduce the detected latch, but have to solve some build-environment problems first.
Also I'm moderately sure the design/code was synthesized before and ran on spartan3/6 and ice40 (with Icecube2) some years ago, but I can't reproduce this ad-hoc.

[tgingold]

A latch is synthesisable, but currently rejected by ghdlsynth.

[tgingold]

I am closing this issue because the bad elaboration order crash is now fixed.
Do not hesitate to open a new issue if you still have a problem with the design.

[rroohhh]

For my case I still get the same bad elaboration order of objects error. I updated my initial message with the updated log and script I used. Here they are again:
Script: https://paste.niemo.de/ubehahuwup.sh
Output: https://paste.niemo.de/raw/lazolamaxo

Also I don't know where you found generic packages, I don't think they are used in this project.

[tgingold]

The elaboration order crash is now fixed. There is a different crash after that; I will have a look at it.

[rroohhh]

Great news, after going through things affected by #93 it seems to atleast not crash or error out. There are still some issues with some cells not being correctly techmapped by yosys, that I will look into further soon.