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[BUG] Missing HECI PCI device and SOF firmware failed to load on ADLP Chrome device #4923

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keqiaozhang opened this issue Oct 27, 2021 · 17 comments
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ADL Applies to Alder Lake platform Boot Firmware boot or code signing related. bug Something isn't working as expected P1 Blocker bugs or important features

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@keqiaozhang
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Describe the bug
I tried to run sof on ADLP chrome device w/ ubuntuOS installed, but firmware failed to boot with error:

[   67.537667] sof-audio-pci-intel-tgl 0000:00:1f.3: error: cl_dsp_init: timeout HDA_DSP_SRAM_REG_ROM_STATUS read

But same firmware binary can boot under ChromeOS and we used the same coreboot image with chrome team(expect the payload for Ubuntu). This is not the key error and I also force prob i915(i915.force_probe=46a8).

To Reproduce
run sof on ADLP chrome device and check the dmesg after booting.

Reproduction Rate
100%

Expected behavior
firmware can load w/o errrors.

Impact
What impact does this issue have on your progress (e.g., annoyance, showstopper)

Environment

  1. latest kernel/sof-dev + sof/main
  2. ADLP Beta release

dmesg

[   66.634634] sof-audio-pci-intel-tgl 0000:00:1f.3: request_firmware intel/sof/community/sof-adl.ri successful
[   66.634653] sof-audio-pci-intel-tgl 0000:00:1f.3: found sof_ext_man header type 1 size 0x1A0
[   66.634669] sof-audio-pci-intel-tgl 0000:00:1f.3: found sof_ext_man header type 6 size 0x20
[   66.634678] sof-audio-pci-intel-tgl 0000:00:1f.3: FW clock config: HPRO
[   66.634684] sof-audio-pci-intel-tgl 0000:00:1f.3: found sof_ext_man header type 0 size 0x50
[   66.634691] sof-audio-pci-intel-tgl 0000:00:1f.3: Firmware info: version 1:8:0-9a35f
[   66.634700] sof-audio-pci-intel-tgl 0000:00:1f.3: Firmware: ABI 3:18:1 Kernel ABI 3:18:0
[   66.634710] sof-audio-pci-intel-tgl 0000:00:1f.3: found sof_ext_man header type 2 size 0x70
[   66.634716] sof-audio-pci-intel-tgl 0000:00:1f.3: Firmware info: used compiler XCC 12:0:8 <RG-2017.8-linux> used optimization flags -O2
[   66.634770] sof-audio-pci-intel-tgl 0000:00:1f.3: found sof_ext_man header type 3 size 0x30
[   66.634778] sof-audio-pci-intel-tgl 0000:00:1f.3: unknown sof_ext_man header type 3 size 0x30
[   66.634784] sof-audio-pci-intel-tgl 0000:00:1f.3: found sof_ext_man header type 4 size 0x20
[   66.634790] sof-audio-pci-intel-tgl 0000:00:1f.3: Firmware: DBG_ABI 5:3:0
[   66.634796] sof-audio-pci-intel-tgl 0000:00:1f.3: found sof_ext_man header type 5 size 0x20
[   66.634802] sof-audio-pci-intel-tgl 0000:00:1f.3: ext_man_get_config_data can hold up to 3 config elements
[   66.634809] sof-audio-pci-intel-tgl 0000:00:1f.3: ext_man_get_config_data get index 0 token 1 val 384
[   66.634817] sof-audio-pci-intel-tgl 0000:00:1f.3: ext_man_get_config_data get index 1 token 2 val 1
[   66.634841] sof-audio-pci-intel-tgl 0000:00:1f.3: ext_man_get_config_data get index 2 token 0 val 0
[   66.634885] sof-audio-pci-intel-tgl 0000:00:1f.3: Debug PCIR: 00000002 at  00000048
[   66.634903] sof-audio-pci-intel-tgl 0000:00:1f.3: Debug PCIW: 00000000 at  00000048
[   66.634928] sof-audio-pci-intel-tgl 0000:00:1f.3: Debug PCIR: 00000000 at  00000044
[   66.634945] sof-audio-pci-intel-tgl 0000:00:1f.3: Debug PCIW: 00000004 at  00000044
[   66.635007] sof-audio-pci-intel-tgl 0000:00:1f.3: booting DSP firmware
[   66.635143] sof-audio-pci-intel-tgl 0000:00:1f.3: period_bytes:0x0
[   66.635151] sof-audio-pci-intel-tgl 0000:00:1f.3: periods:1
[   66.635289] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x160]=0x40000 successful
[   66.635328] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x160]=0x40000 successful
[   66.635337] sof-audio-pci-intel-tgl 0000:00:1f.3: period_bytes:0x0
[   66.635342] sof-audio-pci-intel-tgl 0000:00:1f.3: periods:1
[   66.635451] sof-audio-pci-intel-tgl 0000:00:1f.3: Attempting iteration 0 of Core En/ROM load...
[   66.635464] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 0 : core_mask 1
[   66.635476] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0f successful
[   66.635491] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0e successful
[   66.635500] sof-audio-pci-intel-tgl 0000:00:1f.3: unstall/run core: core_mask = 1
[   66.635512] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 1 : core_mask 1
[   66.635534] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010e0e successful
[   66.635552] sof-audio-pci-intel-tgl 0000:00:1f.3: unstall/run core: core_mask = 1
[   66.635560] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 1 : core_mask 1
[   66.636113] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0xd4]=0x80000000 successful
[   66.936286] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x80000]=0x6000021 timedout
[   66.936307] sof-audio-pci-intel-tgl 0000:00:1f.3: unknown ROM status value 06000021
[   66.936326] sof-audio-pci-intel-tgl 0000:00:1f.3: extended rom status:  0x6000021 0x0 0x0 0x0 0x0 0x0 0x256051f 0x0
[   66.936337] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0f successful
[   66.936346] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf0f successful
[   66.936351] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 0 : core_mask 1
[   66.936355] sof-audio-pci-intel-tgl 0000:00:1f.3: Attempting iteration 1 of Core En/ROM load...
[   66.936360] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 0 : core_mask 1
[   66.936367] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0f successful
[   66.936375] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0e successful
[   66.936380] sof-audio-pci-intel-tgl 0000:00:1f.3: unstall/run core: core_mask = 1
[   66.936386] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 1 : core_mask 1
[   66.936402] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010e0e successful
[   66.936407] sof-audio-pci-intel-tgl 0000:00:1f.3: unstall/run core: core_mask = 1
[   66.936413] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 1 : core_mask 1
[   66.937284] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0xd4]=0x80000000 successful
[   67.237104] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x80000]=0x6000021 timedout
[   67.237116] sof-audio-pci-intel-tgl 0000:00:1f.3: unknown ROM status value 06000021
[   67.237133] sof-audio-pci-intel-tgl 0000:00:1f.3: extended rom status:  0x6000021 0x0 0x0 0x0 0x0 0x0 0x256051f 0x0
[   67.237141] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0f successful
[   67.237149] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf0f successful
[   67.237153] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 0 : core_mask 1
[   67.237157] sof-audio-pci-intel-tgl 0000:00:1f.3: Attempting iteration 2 of Core En/ROM load...
[   67.237161] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 0 : core_mask 1
[   67.237168] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0f successful
[   67.237175] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0e successful
[   67.237179] sof-audio-pci-intel-tgl 0000:00:1f.3: unstall/run core: core_mask = 1
[   67.237184] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 1 : core_mask 1
[   67.237199] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010e0e successful
[   67.237203] sof-audio-pci-intel-tgl 0000:00:1f.3: unstall/run core: core_mask = 1
[   67.237208] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 1 : core_mask 1
[   67.237817] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0xd4]=0x80000000 successful
[   67.537654] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x80000]=0x6000021 timedout
[   67.537667] sof-audio-pci-intel-tgl 0000:00:1f.3: error: cl_dsp_init: timeout HDA_DSP_SRAM_REG_ROM_STATUS read
[   67.537687] sof-audio-pci-intel-tgl 0000:00:1f.3: unknown ROM status value 06000021
[   67.537705] sof-audio-pci-intel-tgl 0000:00:1f.3: error: extended rom status:  0x6000021 0x0 0x0 0x0 0x0 0x0 0x256051f 0x0
[   67.537717] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0f successful
[   67.539021] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf0f successful
[   67.539029] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 0 : core_mask 1
[   67.539034] sof-audio-pci-intel-tgl 0000:00:1f.3: error: dsp init failed after 3 attempts with err: -110
[   67.539121] sof-audio-pci-intel-tgl 0000:00:1f.3: error: failed to reset DSP
[   67.539126] sof-audio-pci-intel-tgl 0000:00:1f.3: error: failed to boot DSP firmware -110
[   67.540084] sof-audio-pci-intel-tgl 0000:00:1f.3: error: sof_probe_work failed err: -110

Full dmesg can be found here:
dmesg.txt

@keqiaozhang keqiaozhang added bug Something isn't working as expected P1 Blocker bugs or important features ADL Applies to Alder Lake platform labels Oct 27, 2021
@lgirdwood
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@keqiaozhang can you bisect, must be something recent, I had a quick look but nothing obvious.

@keqiaozhang
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keqiaozhang commented Nov 2, 2021

This is the first time we run Ubuntu on ADLP Chromebook, I'm not sure whether it's a regression or not. But I did some debugging.

  1. tried same firmware binary, only failed under Ubuntu OS.
  2. tried same coreboot(same coreboot image, but with Ubuntu payload installed) and EC firmware as ChromeOS, still failed under UbuntuOS.
  3. tried chrome kernel 5.10, got same results as above.

I also did some search and found we have a similar issue on CML chromebook before, Same ROM code 06000021. But on CML, issue only happens after S3.

The error status `06000021` reports the ROM is waiting for CSE IPC reset sequence to complete. 
Looks like incorrect timing between CSE and ADSP ROM transition.

#2190 (comment)

@bkokoszx bkokoszx self-assigned this Nov 2, 2021
@mengdonglin mengdonglin added the Boot Firmware boot or code signing related. label Nov 8, 2021
@mwasko
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mwasko commented Nov 8, 2021

The error status 06000021 reports the ROM is waiting for CSE IPC reset sequence to complete.
Looks like incorrect timing between CSE and ADSP ROM transition.

That is correct and in case of unfortunate timing the retry should address the problem. The interesting part is how it actually works on Chrome OS. I would like to recommend investigation of SOF driver routine that load FW and check if there are no differences between Chrome and Ubuntu OS.

Generally from FW perspective there is not much we can do about it.

@plbossart
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@mwasko there's no difference at the driver level see above the chrome kernel used in Ubuntu also has a problem

And we already retry 3 times before throwing an error, see above.

@mwasko
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mwasko commented Nov 9, 2021

@mwasko there's no difference at the driver level see above the chrome kernel used in Ubuntu also has a problem

And we already retry 3 times before throwing an error, see above.

In that case you need to contact BIOS/CSME team for support.

@lgirdwood
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@keqiaozhang is this failure from power ON or reboot. Just thinking if this needs @keyonjie IMR PR

@keqiaozhang
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@lgirdwood this failure is from power on, so I don't think IMR PR will help.

@keqiaozhang
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I run to this issue on another ADLP Chrome device(I2S mode) with same rom error:

[    4.140129] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 1 : core_mask 1
[    4.140643] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0xd4]=0x80000000 successful
[    4.441081] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x80000]=0x6000021 timedout
[    4.441089] sof-audio-pci-intel-tgl 0000:00:1f.3: error: cl_dsp_init: timeout HDA_DSP_SRAM_REG_ROM_STATUS read
[    4.441097] sof-audio-pci-intel-tgl 0000:00:1f.3: ------------[ DSP dump start ]------------
[    4.441100] sof-audio-pci-intel-tgl 0000:00:1f.3: Boot iteration failed: 3/3
[    4.441102] sof-audio-pci-intel-tgl 0000:00:1f.3: fw_state: SOF_FW_BOOT_IN_PROGRESS (2)
[    4.441109] sof-audio-pci-intel-tgl 0000:00:1f.3: unknown ROM status value 06000021
[    4.441121] sof-audio-pci-intel-tgl 0000:00:1f.3: extended rom status:  0x6000021 0x0 0x0 0x0 0x0 0x0 0x256051f 0x0
[    4.441123] sof-audio-pci-intel-tgl 0000:00:1f.3: ------------[ DSP dump end ]------------
[    4.441129] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf010f0f successful
[    4.441586] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0xf0f successful
[    4.441590] sof-audio-pci-intel-tgl 0000:00:1f.3: DSP core(s) enabled? 0 : core_mask 1
[    4.441594] sof-audio-pci-intel-tgl 0000:00:1f.3: error: dsp init failed after 3 attempts with err: -110
[    4.441639] sof-audio-pci-intel-tgl 0000:00:1f.3: ------------[ DSP dump start ]------------
[    4.441642] sof-audio-pci-intel-tgl 0000:00:1f.3: Failed to start DSP
[    4.441645] sof-audio-pci-intel-tgl 0000:00:1f.3: fw_state: SOF_FW_BOOT_IN_PROGRESS (2)
[    4.441650] sof-audio-pci-intel-tgl 0000:00:1f.3: unknown ROM status value 01009701
[    4.441673] sof-audio-pci-intel-tgl 0000:00:1f.3: extended rom status:  0x1009701 0x1d003c 0x1 0x0 0x10000 0xc00 0x180030 0x0
[    4.441676] sof-audio-pci-intel-tgl 0000:00:1f.3: ------------[ DSP dump end ]------------
[    4.441678] sof-audio-pci-intel-tgl 0000:00:1f.3: error: failed to boot DSP firmware -110
[    4.441681] sof-audio-pci-intel-tgl 0000:00:1f.3: fw_state change: 2 -> 3
[    4.492690] sof-audio-pci-intel-tgl 0000:00:1f.3: FW Poll Status: reg[0x4]=0x1d003c timedout
[    4.492699] sof-audio-pci-intel-tgl 0000:00:1f.3: error: hda_dsp_core_reset_enter: timeout on HDA_DSP_REG_ADSPCS read
[    4.492706] sof-audio-pci-intel-tgl 0000:00:1f.3: error: dsp core reset failed: core_mask 1
[    4.493536] sof-audio-pci-intel-tgl 0000:00:1f.3: fw_state change: 3 -> 0
[    4.493610] sof-audio-pci-intel-tgl 0000:00:1f.3: error: sof_probe_work failed err: -110

The rom status 0x6000021 means FSR_ROM_CSE_IPC_RESET_PHASE_1
Specifically, the CSME did not respond for this IPC in the authentication flow: FSR_ROM_CSE_IPC_RESET_PHASE_1 Ox21.

I'm checking this issue with coreboot team.

@keqiaozhang
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The latest update from CSME team:
the HECI device is not enumerated in your ubuntu system, so basically communication channel with CSE is down. Hence, you are seeing the errors

@mengdonglin mengdonglin changed the title [BUG] SOF firmware failed to load on ADLP Chrome device [BUG] Missing HECI PCI device and SOF firmware failed to load on ADLP Chrome device Dec 6, 2021
@marc-hb
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marc-hb commented Dec 10, 2021

the HECI device is not enumerated in your ubuntu system,

What does "enumerated" mean here? Enumerated by whom? Where can this enumeration be seen or seen missing?

The interesting part is how it actually works on Chrome OS.

Indeed, with the same coreboot and same kernel even! Pure user space code should not affect low level CSE communication channels like this, this does not make sense.

@keqiaozhang
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Coreboot team has found the root cause of this issue.
The GBB (Google Binary Block) flags are defined in the vboot_reference source, one option called "GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC", if this option is enabled in coreboot(enable the EC sync), the OS will enters to recovery mode, then the CSE will be disabled and cannot send End-of-Post (EOP) message.

The solution is that we can modify the GBB flags value of coreboot image under ChromeOS to disable the EC sync.
/usr/share/vboot/bin/set_gbb_flags.sh -f <CB_ImaGE> 0x238
Then flash the CB and reboot.

@marc-hb
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marc-hb commented Jan 5, 2022

if this option is enabled in coreboot(enable the EC sync), the OS will enters to recovery mode

EC sync (update) is a normal security feature so I don't understand why the Chromebook would enter recovery mode when using it. Recovery mode was never mentioned in this bug before. Also, the OS is not involved in recovery because recovery mode is designed to recover the OS.

the OS will enters to recovery mode, then the CSE will be disabled

How does that follow?

/usr/share/vboot/bin/set_gbb_flags.sh -f <CB_ImaGE> 0x238

This disables the EC sync flag 0x200 but resets all other (more or less unknown) flags too
https://github.com/coreboot/coreboot/blob/master/src/security/vboot/Makefile.inc#L215
Better read the previous values first and add 0x200 only.
https://chromium.googlesource.com/chromiumos/docs/+/HEAD/firmware_test_manual.md#Update-GBB-Flags-AKA-extend-recovery-screen-timeout

Then flash the CB and reboot.

There's no need to flash coreboot after updating the GBB flags.


https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/README.md#Preventing-the-RW-EC-firmware-from-being-overwritten-by-Software-Sync-at-boot

A feature called “Software Sync” keeps a copy of the read-write (RW) EC firmware in the RW part of the system firmware image. At boot, if the RW EC firmware doesn't match the copy in the system firmware, the EC’s RW section is re-flashed. While this is great for normal use as it makes updating the EC and system firmware a unified operation, it can be a challenge for EC firmware development. To disable software sync a flag can be set in the system firmware. Run the following commands from a shell on the device to disable Software Sync and turn on other developer-friendly flags (note that write protect must be disabled for this to work):
/usr/share/vboot/bin/set_gbb_flags.sh 0x239

@marc-hb marc-hb reopened this Jan 5, 2022
@keqiaozhang
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Better read the previous values first and add 0x200 only.

The previous GBB set flags are: 0x00000239

How does that follow?

/usr/share/vboot/bin/set_gbb_flags.sh -f <CB_ImaGE> 0x238

This is used to change the GBB flags for the Tianocore Coreboot.

Then flash the CB and reboot.

There's no need to flash coreboot after updating the GBB flags.

Because set_gbb_flags is only available under ChromeOS, but we aim to flash the coreboot with Tianocore to support UbuntuOS. So we change the GBB flags for the Tianocore coreboot and flash this coreboot image to install UbuntuOS.
So this is more like a workaround, I think they can disable the EC sync when building the Tianocore Coreboot.

@marc-hb
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marc-hb commented Jan 6, 2022

The previous GBB set flags are: 0x00000239

The previous flags can be whatever. To change one line in a configuration file no one overwrites the entire configuration file (makes it impossible to know what fixed what).

This is used to change the GBB flags for the Tianocore Coreboot.

This is the first time Tianocore is mentioned in this bug. Previously it was:

tried same coreboot(same coreboot image, but with Ubuntu payload installed) and EC firmware as ChromeOS, still failed under UbuntuOS.

Still not clear how the EC version or update affects the CSME or recovery mode. It's all very nebulous https://www.google.com/search?q=programming+by+coincidence

@mengdonglin
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This issue was fixed by coreboot. Close it.

@Espionage724
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Espionage724 commented Jul 2, 2023

I'm on an unrelated platform, but I ran into this after disabling MEI and found this ticket. Maybe this info might be useful to someone.

I'm on Coffee Lake and I disabled Intel MEI via HAP bit so the HECI device isn't present. My platform defaults to the audio DSP disabled and uses a generic HDA driver on Windows with Waves extensions.

I intentionally enabled the audio DSP (0xF48 to 1) and set it to Intel SST mode (non UAA compliance, 0xF49 to 0). Prior to disabling MEI, audio with SST worked fine on Windows (after some forced driver installs) and out-the-box on Linux and I noticed in dmesg some new firmware loading info.

Now with MEI disabled, I get this in dmesg along with no audio (kernel 6.3.8 Fedora 38):

[   10.083084] sof-audio-pci-intel-cnl 0000:00:1f.3: DSP detected with PCI class/subclass/prog-if info 0x040100
[   10.083193] sof-audio-pci-intel-cnl 0000:00:1f.3: Digital mics found on Skylake+ platform, using SOF driver
[   10.083203] sof-audio-pci-intel-cnl 0000:00:1f.3: enabling device (0000 -> 0002)
[   10.083383] sof-audio-pci-intel-cnl 0000:00:1f.3: DSP detected with PCI class/subclass/prog-if 0x040100
[   10.083453] sof-audio-pci-intel-cnl 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
[   10.090121] sof-audio-pci-intel-cnl 0000:00:1f.3: use msi interrupt mode
[   10.168085] sof-audio-pci-intel-cnl 0000:00:1f.3: hda codecs found, mask 5
[   10.168089] sof-audio-pci-intel-cnl 0000:00:1f.3: using HDA machine driver skl_hda_dsp_generic now
[   10.168093] sof-audio-pci-intel-cnl 0000:00:1f.3: DMICs detected in NHLT tables: 4
[   10.187480] sof-audio-pci-intel-cnl 0000:00:1f.3: Firmware info: version 2:2:0-57864
[   10.187483] sof-audio-pci-intel-cnl 0000:00:1f.3: Firmware: ABI 3:22:1 Kernel ABI 3:23:0
[   10.187489] sof-audio-pci-intel-cnl 0000:00:1f.3: unknown sof_ext_man header type 3 size 0x30
[   11.093018] sof-audio-pci-intel-cnl 0000:00:1f.3: cl_dsp_init: timeout with rom_status_reg (0x80000) read
[   11.093025] sof-audio-pci-intel-cnl 0000:00:1f.3: ------------[ DSP dump start ]------------
[   11.093027] sof-audio-pci-intel-cnl 0000:00:1f.3: Boot iteration failed: 3/3
[   11.093028] sof-audio-pci-intel-cnl 0000:00:1f.3: fw_state: SOF_FW_BOOT_IN_PROGRESS (2)
[   11.093038] sof-audio-pci-intel-cnl 0000:00:1f.3: 0x06000021: module: ROM, state: CSE_IPC_RESET_PHASE_1, waiting for: CSE_CSR, running
[   11.093058] sof-audio-pci-intel-cnl 0000:00:1f.3: extended rom status:  0x6000021 0x0 0x0 0x0 0x0 0x0 0x183011b 0x0
[   11.093060] sof-audio-pci-intel-cnl 0000:00:1f.3: ------------[ DSP dump end ]------------
[   11.093580] sof-audio-pci-intel-cnl 0000:00:1f.3: error: dsp init failed after 3 attempts with err: -110
[   11.093592] sof-audio-pci-intel-cnl 0000:00:1f.3: Failed to start DSP
[   11.093593] sof-audio-pci-intel-cnl 0000:00:1f.3: error: failed to boot DSP firmware -110
[   11.144019] sof-audio-pci-intel-cnl 0000:00:1f.3: error: hda_dsp_core_reset_enter: timeout on HDA_DSP_REG_ADSPCS read
[   11.144023] sof-audio-pci-intel-cnl 0000:00:1f.3: error: dsp core reset failed: core_mask f
[   11.144182] sof-audio-pci-intel-cnl 0000:00:1f.3: error: sof_probe_work failed err: -110

I don't have a particular need for the DSP and was mostly just experimenting with different setting; I can just re-disable the DSP and have no problems on my platform. I've heard of some interesting issues when disabling ME, but I wasn't expecting audio to be tied to it :p

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marc-hb commented Jul 3, 2023

I've heard of some interesting issues when disabling ME, but I wasn't expecting audio to be tied to it :p

https://thesofproject.github.io/latest/getting_started/intel_debug/introduction.html#firmware-binary

The Intel ME (Management Engine) is responsible for authentication of the firmware, whether it is signed by an Intel production key (consumer products), a community key (open development systems and Chromebooks since Gemini Lake) or an OEM key. If the Intel ME is disabled by an OEM, or disabled by user-accessible BIOS options, the firmware authentication will fail and the firmware boot will not complete. If the ME is disabled by the OEM, the only solution is to fall-back to the legacy HDAudio driver.

From https://www.intel.com/content/dam/www/public/us/en/security-advisory/documents/intel-csme-security-white-paper.pdf

Intel® CSME enables secure loading and execution of Intel-signed DAL (Intel® Dynamic Application Loader) applets and secure firmware loading of other platform-firmware components, such as TBT (ThunderboltTM), Type-C, Sensor Solution FW, etc.

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