body of modules is not indented

[ry]

Is there a way to force iStyle to indent the body of modules rather than putting it in column zero?

Example:

module picosoc_mem #(
  parameter integer WORDS = 256
) (
  input clk,
  input [3:0] wen,
  input [21:0] addr,
  input [31:0] wdata,
  output reg [31:0] rdata
);
  reg [31:0] mem [0:WORDS-1];

  always @(posedge clk) begin
    rdata <= mem[addr];
    if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
    if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
    if (wen[2]) mem[addr][23:16] <= wdata[23:16];
    if (wen[3]) mem[addr][31:24] <= wdata[31:24];
  end
endmodule

[thomasrussellmurphy]

Will you please provide before/after examples for your desired format and which existing iStyle formatting options you've tried using?

[ry]

If I have this file

module top();
reg a = 1;
endmodule;

And I run it through iStyle: iStyle -n foo.v. I want the body of the module to be indented two spaces:

module top();
  reg a = 1;
endmodule;

but that is not the what I get from iStyle

[thomasrussellmurphy]

Please ensure that the existing, documented features do not meet your current needs. Custom formatting is provided by additional flags: https://github.com/thomasrussellmurphy/istyle-verilog-formatter#indentation-options

[ry]

Are you saying this is already supported? I went through many combinations of flags but was not able to get that result.

[thomasrussellmurphy]

Please keep in mind that, despite being the repository owner, I am not the original author of this. Since your initial request did not mention your test cases and I am insufficiently familiar with the formatting capabilities, I wanted to check.

I would recommend checking the implementation of --indent-blocks and --indent-brackets to see if that logic could be conditionally applied to the module body as a whole. Pull requests welcomed.

[thomasrussellmurphy]

Has the January change helped with this?