/
MpService.c
2233 lines (1869 loc) · 66.2 KB
/
MpService.c
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/** @file
SMM MP service implementation
Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PiSmmCpuDxeSmm.h"
//
// Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)
//
MTRR_SETTINGS gSmiMtrrs;
UINT64 gPhyMask;
SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL;
UINTN mSmmMpSyncDataSize;
SMM_CPU_SEMAPHORES mSmmCpuSemaphores;
UINTN mSemaphoreSize;
SPIN_LOCK *mPFLock = NULL;
SMM_CPU_SYNC_MODE mCpuSmmSyncMode;
BOOLEAN mMachineCheckSupported = FALSE;
MM_COMPLETION mSmmStartupThisApToken;
//
// Processor specified by mPackageFirstThreadIndex[PackageIndex] will do the package-scope register check.
//
UINT32 *mPackageFirstThreadIndex = NULL;
extern UINTN mSmmShadowStackSize;
/**
Performs an atomic compare exchange operation to get semaphore.
The compare exchange operation must be performed using
MP safe mechanisms.
@param Sem IN: 32-bit unsigned integer
OUT: original integer - 1
@return Original integer - 1
**/
UINT32
WaitForSemaphore (
IN OUT volatile UINT32 *Sem
)
{
UINT32 Value;
for ( ; ;) {
Value = *Sem;
if ((Value != 0) &&
(InterlockedCompareExchange32 (
(UINT32 *)Sem,
Value,
Value - 1
) == Value))
{
break;
}
CpuPause ();
}
return Value - 1;
}
/**
Performs an atomic compare exchange operation to release semaphore.
The compare exchange operation must be performed using
MP safe mechanisms.
@param Sem IN: 32-bit unsigned integer
OUT: original integer + 1
@return Original integer + 1
**/
UINT32
ReleaseSemaphore (
IN OUT volatile UINT32 *Sem
)
{
UINT32 Value;
do {
Value = *Sem;
} while (Value + 1 != 0 &&
InterlockedCompareExchange32 (
(UINT32 *)Sem,
Value,
Value + 1
) != Value);
return Value + 1;
}
/**
Performs an atomic compare exchange operation to lock semaphore.
The compare exchange operation must be performed using
MP safe mechanisms.
@param Sem IN: 32-bit unsigned integer
OUT: -1
@return Original integer
**/
UINT32
LockdownSemaphore (
IN OUT volatile UINT32 *Sem
)
{
UINT32 Value;
do {
Value = *Sem;
} while (InterlockedCompareExchange32 (
(UINT32 *)Sem,
Value,
(UINT32)-1
) != Value);
return Value;
}
/**
Wait all APs to performs an atomic compare exchange operation to release semaphore.
@param NumberOfAPs AP number
**/
VOID
WaitForAllAPs (
IN UINTN NumberOfAPs
)
{
UINTN BspIndex;
BspIndex = mSmmMpSyncData->BspIndex;
while (NumberOfAPs-- > 0) {
WaitForSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
}
}
/**
Performs an atomic compare exchange operation to release semaphore
for each AP.
**/
VOID
ReleaseAllAPs (
VOID
)
{
UINTN Index;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (IsPresentAp (Index)) {
ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run);
}
}
}
/**
Check whether the index of CPU perform the package level register
programming during System Management Mode initialization.
The index of Processor specified by mPackageFirstThreadIndex[PackageIndex]
will do the package-scope register programming.
@param[in] CpuIndex Processor Index.
@retval TRUE Perform the package level register programming.
@retval FALSE Don't perform the package level register programming.
**/
BOOLEAN
IsPackageFirstThread (
IN UINTN CpuIndex
)
{
UINT32 PackageIndex;
PackageIndex = gSmmCpuPrivate->ProcessorInfo[CpuIndex].Location.Package;
ASSERT (mPackageFirstThreadIndex != NULL);
//
// Set the value of mPackageFirstThreadIndex[PackageIndex].
// The package-scope register are checked by the first processor (CpuIndex) in Package.
//
// If mPackageFirstThreadIndex[PackageIndex] equals to (UINT32)-1, then update
// to current CpuIndex. If it doesn't equal to (UINT32)-1, don't change it.
//
if (mPackageFirstThreadIndex[PackageIndex] == (UINT32)-1) {
mPackageFirstThreadIndex[PackageIndex] = (UINT32)CpuIndex;
}
return (BOOLEAN)(mPackageFirstThreadIndex[PackageIndex] == CpuIndex);
}
/**
Returns the Number of SMM Delayed & Blocked & Disabled Thread Count.
@param[in,out] DelayedCount The Number of SMM Delayed Thread Count.
@param[in,out] BlockedCount The Number of SMM Blocked Thread Count.
@param[in,out] DisabledCount The Number of SMM Disabled Thread Count.
**/
VOID
GetSmmDelayedBlockedDisabledCount (
IN OUT UINT32 *DelayedCount,
IN OUT UINT32 *BlockedCount,
IN OUT UINT32 *DisabledCount
)
{
UINTN Index;
for (Index = 0; Index < mNumberOfCpus; Index++) {
if (IsPackageFirstThread (Index)) {
if (DelayedCount != NULL) {
*DelayedCount += (UINT32)SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed);
}
if (BlockedCount != NULL) {
*BlockedCount += (UINT32)SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked);
}
if (DisabledCount != NULL) {
*DisabledCount += (UINT32)SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable);
}
}
}
}
/**
Checks if all CPUs (except Blocked & Disabled) have checked in for this SMI run
@retval TRUE if all CPUs the have checked in.
@retval FALSE if at least one Normal AP hasn't checked in.
**/
BOOLEAN
AllCpusInSmmExceptBlockedDisabled (
VOID
)
{
UINT32 BlockedCount;
UINT32 DisabledCount;
BlockedCount = 0;
DisabledCount = 0;
//
// Check to make sure mSmmMpSyncData->Counter is valid and not locked.
//
ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);
//
// Check whether all CPUs in SMM.
//
if (*mSmmMpSyncData->Counter == mNumberOfCpus) {
return TRUE;
}
//
// Check for the Blocked & Disabled Exceptions Case.
//
GetSmmDelayedBlockedDisabledCount (NULL, &BlockedCount, &DisabledCount);
//
// *mSmmMpSyncData->Counter might be updated by all APs concurrently. The value
// can be dynamic changed. If some Aps enter the SMI after the BlockedCount &
// DisabledCount check, then the *mSmmMpSyncData->Counter will be increased, thus
// leading the *mSmmMpSyncData->Counter + BlockedCount + DisabledCount > mNumberOfCpus.
// since the BlockedCount & DisabledCount are local variable, it's ok here only for
// the checking of all CPUs In Smm.
//
if (*mSmmMpSyncData->Counter + BlockedCount + DisabledCount >= mNumberOfCpus) {
return TRUE;
}
return FALSE;
}
/**
Has OS enabled Lmce in the MSR_IA32_MCG_EXT_CTL
@retval TRUE Os enable lmce.
@retval FALSE Os not enable lmce.
**/
BOOLEAN
IsLmceOsEnabled (
VOID
)
{
MSR_IA32_MCG_CAP_REGISTER McgCap;
MSR_IA32_FEATURE_CONTROL_REGISTER FeatureCtrl;
MSR_IA32_MCG_EXT_CTL_REGISTER McgExtCtrl;
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
if (McgCap.Bits.MCG_LMCE_P == 0) {
return FALSE;
}
FeatureCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
if (FeatureCtrl.Bits.LmceOn == 0) {
return FALSE;
}
McgExtCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
return (BOOLEAN)(McgExtCtrl.Bits.LMCE_EN == 1);
}
/**
Return if Local machine check exception signaled.
Indicates (when set) that a local machine check exception was generated. This indicates that the current machine-check event was
delivered to only the logical processor.
@retval TRUE LMCE was signaled.
@retval FALSE LMCE was not signaled.
**/
BOOLEAN
IsLmceSignaled (
VOID
)
{
MSR_IA32_MCG_STATUS_REGISTER McgStatus;
McgStatus.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
return (BOOLEAN)(McgStatus.Bits.LMCE_S == 1);
}
/**
Given timeout constraint, wait for all APs to arrive, and insure when this function returns, no AP will execute normal mode code before
entering SMM, except SMI disabled APs.
**/
VOID
SmmWaitForApArrival (
VOID
)
{
UINT64 Timer;
UINTN Index;
BOOLEAN LmceEn;
BOOLEAN LmceSignal;
UINT32 DelayedCount;
UINT32 BlockedCount;
DelayedCount = 0;
BlockedCount = 0;
ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);
LmceEn = FALSE;
LmceSignal = FALSE;
if (mMachineCheckSupported) {
LmceEn = IsLmceOsEnabled ();
LmceSignal = IsLmceSignaled ();
}
//
// Platform implementor should choose a timeout value appropriately:
// - The timeout value should balance the SMM time constrains and the likelihood that delayed CPUs are excluded in the SMM run. Note
// the SMI Handlers must ALWAYS take into account the cases that not all APs are available in an SMI run.
// - The timeout value must, in the case of 2nd timeout, be at least long enough to give time for all APs to receive the SMI IPI
// and either enter SMM or buffer the SMI, to insure there is no CPU running normal mode code when SMI handling starts. This will
// be TRUE even if a blocked CPU is brought out of the blocked state by a normal mode CPU (before the normal mode CPU received the
// SMI IPI), because with a buffered SMI, and CPU will enter SMM immediately after it is brought out of the blocked state.
// - The timeout value must be longer than longest possible IO operation in the system
//
//
// Sync with APs 1st timeout
//
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal);
)
{
mSmmMpSyncData->AllApArrivedWithException = AllCpusInSmmExceptBlockedDisabled ();
if (mSmmMpSyncData->AllApArrivedWithException) {
break;
}
CpuPause ();
}
//
// Not all APs have arrived, so we need 2nd round of timeout. IPIs should be sent to ALL none present APs,
// because:
// a) Delayed AP may have just come out of the delayed state. Blocked AP may have just been brought out of blocked state by some AP running
// normal mode code. These APs need to be guaranteed to have an SMI pending to insure that once they are out of delayed / blocked state, they
// enter SMI immediately without executing instructions in normal mode. Note traditional flow requires there are no APs doing normal mode
// work while SMI handling is on-going.
// b) As a consequence of SMI IPI sending, (spurious) SMI may occur after this SMM run.
// c) ** NOTE **: Use SMI disabling feature VERY CAREFULLY (if at all) for traditional flow, because a processor in SMI-disabled state
// will execute normal mode code, which breaks the traditional SMI handlers' assumption that no APs are doing normal
// mode work while SMI handling is on-going.
// d) We don't add code to check SMI disabling status to skip sending IPI to SMI disabled APs, because:
// - In traditional flow, SMI disabling is discouraged.
// - In relaxed flow, CheckApArrival() will check SMI disabling status before calling this function.
// In both cases, adding SMI-disabling checking code increases overhead.
//
if (*mSmmMpSyncData->Counter < mNumberOfCpus) {
//
// Send SMI IPIs to bring outside processors in
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) {
SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
}
}
//
// Sync with APs 2nd timeout.
//
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer);
)
{
mSmmMpSyncData->AllApArrivedWithException = AllCpusInSmmExceptBlockedDisabled ();
if (mSmmMpSyncData->AllApArrivedWithException) {
break;
}
CpuPause ();
}
}
if (!mSmmMpSyncData->AllApArrivedWithException) {
//
// Check for the Blocked & Delayed Case.
//
GetSmmDelayedBlockedDisabledCount (&DelayedCount, &BlockedCount, NULL);
DEBUG ((DEBUG_INFO, "SmmWaitForApArrival: Delayed AP Count = %d, Blocked AP Count = %d\n", DelayedCount, BlockedCount));
}
return;
}
/**
Replace OS MTRR's with SMI MTRR's.
@param CpuIndex Processor Index
**/
VOID
ReplaceOSMtrrs (
IN UINTN CpuIndex
)
{
SmmCpuFeaturesDisableSmrr ();
//
// Replace all MTRRs registers
//
MtrrSetAllMtrrs (&gSmiMtrrs);
}
/**
Wheck whether task has been finished by all APs.
@param BlockMode Whether did it in block mode or non-block mode.
@retval TRUE Task has been finished by all APs.
@retval FALSE Task not has been finished by all APs.
**/
BOOLEAN
WaitForAllAPsNotBusy (
IN BOOLEAN BlockMode
)
{
UINTN Index;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
//
// Ignore BSP and APs which not call in SMM.
//
if (!IsPresentAp (Index)) {
continue;
}
if (BlockMode) {
AcquireSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
} else {
if (AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) {
ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
} else {
return FALSE;
}
}
}
return TRUE;
}
/**
Check whether it is an present AP.
@param CpuIndex The AP index which calls this function.
@retval TRUE It's a present AP.
@retval TRUE This is not an AP or it is not present.
**/
BOOLEAN
IsPresentAp (
IN UINTN CpuIndex
)
{
return ((CpuIndex != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) &&
*(mSmmMpSyncData->CpuData[CpuIndex].Present));
}
/**
Clean up the status flags used during executing the procedure.
@param CpuIndex The AP index which calls this function.
**/
VOID
ReleaseToken (
IN UINTN CpuIndex
)
{
PROCEDURE_TOKEN *Token;
Token = mSmmMpSyncData->CpuData[CpuIndex].Token;
if (InterlockedDecrement (&Token->RunningApCount) == 0) {
ReleaseSpinLock (Token->SpinLock);
}
mSmmMpSyncData->CpuData[CpuIndex].Token = NULL;
}
/**
Free the tokens in the maintained list.
**/
VOID
ResetTokens (
VOID
)
{
//
// Reset the FirstFreeToken to the beginning of token list upon exiting SMI.
//
gSmmCpuPrivate->FirstFreeToken = GetFirstNode (&gSmmCpuPrivate->TokenList);
}
/**
SMI handler for BSP.
@param CpuIndex BSP processor Index
@param SyncMode SMM MP sync mode
**/
VOID
BSPHandler (
IN UINTN CpuIndex,
IN SMM_CPU_SYNC_MODE SyncMode
)
{
UINTN Index;
MTRR_SETTINGS Mtrrs;
UINTN ApCount;
BOOLEAN ClearTopLevelSmiResult;
UINTN PresentCount;
ASSERT (CpuIndex == mSmmMpSyncData->BspIndex);
ApCount = 0;
//
// Flag BSP's presence
//
*mSmmMpSyncData->InsideSmm = TRUE;
//
// Initialize Debug Agent to start source level debug in BSP handler
//
InitializeDebugAgent (DEBUG_AGENT_INIT_ENTER_SMI, NULL, NULL);
//
// Mark this processor's presence
//
*(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE;
//
// Clear platform top level SMI status bit before calling SMI handlers. If
// we cleared it after SMI handlers are run, we would miss the SMI that
// occurs after SMI handlers are done and before SMI status bit is cleared.
//
ClearTopLevelSmiResult = ClearTopLevelSmiStatus ();
ASSERT (ClearTopLevelSmiResult == TRUE);
//
// Set running processor index
//
gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu = CpuIndex;
//
// If Traditional Sync Mode or need to configure MTRRs: gather all available APs.
//
if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Wait for APs to arrive
//
SmmWaitForApArrival ();
//
// Lock the counter down and retrieve the number of APs
//
*mSmmMpSyncData->AllCpusInSync = TRUE;
ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;
//
// Wait for all APs to get ready for programming MTRRs
//
WaitForAllAPs (ApCount);
if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Signal all APs it's time for backup MTRRs
//
ReleaseAllAPs ();
//
// WaitForSemaphore() may wait for ever if an AP happens to enter SMM at
// exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has been set
// to a large enough value to avoid this situation.
// Note: For HT capable CPUs, threads within a core share the same set of MTRRs.
// We do the backup first and then set MTRR to avoid race condition for threads
// in the same core.
//
MtrrGetAllMtrrs (&Mtrrs);
//
// Wait for all APs to complete their MTRR saving
//
WaitForAllAPs (ApCount);
//
// Let all processors program SMM MTRRs together
//
ReleaseAllAPs ();
//
// WaitForSemaphore() may wait for ever if an AP happens to enter SMM at
// exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has been set
// to a large enough value to avoid this situation.
//
ReplaceOSMtrrs (CpuIndex);
//
// Wait for all APs to complete their MTRR programming
//
WaitForAllAPs (ApCount);
}
}
//
// The BUSY lock is initialized to Acquired state
//
AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
//
// Perform the pre tasks
//
PerformPreTasks ();
//
// Invoke SMM Foundation EntryPoint with the processor information context.
//
gSmmCpuPrivate->SmmCoreEntry (&gSmmCpuPrivate->SmmCoreEntryContext);
//
// Make sure all APs have completed their pending none-block tasks
//
WaitForAllAPsNotBusy (TRUE);
//
// Perform the remaining tasks
//
PerformRemainingTasks ();
//
// If Relaxed-AP Sync Mode: gather all available APs after BSP SMM handlers are done, and
// make those APs to exit SMI synchronously. APs which arrive later will be excluded and
// will run through freely.
//
if ((SyncMode != SmmCpuSyncModeTradition) && !SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Lock the counter down and retrieve the number of APs
//
*mSmmMpSyncData->AllCpusInSync = TRUE;
ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;
//
// Make sure all APs have their Present flag set
//
while (TRUE) {
PresentCount = 0;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (*(mSmmMpSyncData->CpuData[Index].Present)) {
PresentCount++;
}
}
if (PresentCount > ApCount) {
break;
}
}
}
//
// Notify all APs to exit
//
*mSmmMpSyncData->InsideSmm = FALSE;
ReleaseAllAPs ();
//
// Wait for all APs to complete their pending tasks
//
WaitForAllAPs (ApCount);
if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Signal APs to restore MTRRs
//
ReleaseAllAPs ();
//
// Restore OS MTRRs
//
SmmCpuFeaturesReenableSmrr ();
MtrrSetAllMtrrs (&Mtrrs);
//
// Wait for all APs to complete MTRR programming
//
WaitForAllAPs (ApCount);
}
//
// Stop source level debug in BSP handler, the code below will not be
// debugged.
//
InitializeDebugAgent (DEBUG_AGENT_INIT_EXIT_SMI, NULL, NULL);
//
// Signal APs to Reset states/semaphore for this processor
//
ReleaseAllAPs ();
//
// Perform pending operations for hot-plug
//
SmmCpuUpdate ();
//
// Clear the Present flag of BSP
//
*(mSmmMpSyncData->CpuData[CpuIndex].Present) = FALSE;
//
// Gather APs to exit SMM synchronously. Note the Present flag is cleared by now but
// WaitForAllAps does not depend on the Present flag.
//
WaitForAllAPs (ApCount);
//
// Reset the tokens buffer.
//
ResetTokens ();
//
// Reset BspIndex to -1, meaning BSP has not been elected.
//
if (FeaturePcdGet (PcdCpuSmmEnableBspElection)) {
mSmmMpSyncData->BspIndex = (UINT32)-1;
}
//
// Allow APs to check in from this point on
//
*mSmmMpSyncData->Counter = 0;
*mSmmMpSyncData->AllCpusInSync = FALSE;
mSmmMpSyncData->AllApArrivedWithException = FALSE;
}
/**
SMI handler for AP.
@param CpuIndex AP processor Index.
@param ValidSmi Indicates that current SMI is a valid SMI or not.
@param SyncMode SMM MP sync mode.
**/
VOID
APHandler (
IN UINTN CpuIndex,
IN BOOLEAN ValidSmi,
IN SMM_CPU_SYNC_MODE SyncMode
)
{
UINT64 Timer;
UINTN BspIndex;
MTRR_SETTINGS Mtrrs;
EFI_STATUS ProcedureStatus;
//
// Timeout BSP
//
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) &&
!(*mSmmMpSyncData->InsideSmm);
)
{
CpuPause ();
}
if (!(*mSmmMpSyncData->InsideSmm)) {
//
// BSP timeout in the first round
//
if (mSmmMpSyncData->BspIndex != -1) {
//
// BSP Index is known
// Existing AP is in SMI now but BSP not in, so, try bring BSP in SMM.
//
BspIndex = mSmmMpSyncData->BspIndex;
ASSERT (CpuIndex != BspIndex);
//
// Send SMI IPI to bring BSP in
//
SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[BspIndex].ProcessorId);
//
// Now clock BSP for the 2nd time
//
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) &&
!(*mSmmMpSyncData->InsideSmm);
)
{
CpuPause ();
}
if (!(*mSmmMpSyncData->InsideSmm)) {
//
// Give up since BSP is unable to enter SMM
// and signal the completion of this AP
// Reduce the mSmmMpSyncData->Counter!
//
WaitForSemaphore (mSmmMpSyncData->Counter);
return;
}
} else {
//
// Don't know BSP index. Give up without sending IPI to BSP.
// Reduce the mSmmMpSyncData->Counter!
//
WaitForSemaphore (mSmmMpSyncData->Counter);
return;
}
}
//
// BSP is available
//
BspIndex = mSmmMpSyncData->BspIndex;
ASSERT (CpuIndex != BspIndex);
//
// Mark this processor's presence
//
*(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE;
if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Notify BSP of arrival at this point
//
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
}
if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Wait for the signal from BSP to backup MTRRs
//
WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
//
// Backup OS MTRRs
//
MtrrGetAllMtrrs (&Mtrrs);
//
// Signal BSP the completion of this AP
//
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
//
// Wait for BSP's signal to program MTRRs
//
WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
//
// Replace OS MTRRs with SMI MTRRs
//
ReplaceOSMtrrs (CpuIndex);
//
// Signal BSP the completion of this AP
//
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
}
while (TRUE) {
//
// Wait for something to happen
//
WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
//
// Check if BSP wants to exit SMM
//
if (!(*mSmmMpSyncData->InsideSmm)) {
break;
}
//
// BUSY should be acquired by SmmStartupThisAp()
//
ASSERT (
!AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[CpuIndex].Busy)
);
//
// Invoke the scheduled procedure
//
ProcedureStatus = (*mSmmMpSyncData->CpuData[CpuIndex].Procedure)(
(VOID *)mSmmMpSyncData->CpuData[CpuIndex].Parameter
);
if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) {
*mSmmMpSyncData->CpuData[CpuIndex].Status = ProcedureStatus;
}
if (mSmmMpSyncData->CpuData[CpuIndex].Token != NULL) {
ReleaseToken (CpuIndex);
}
//
// Release BUSY
//
ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
}
if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Notify BSP the readiness of this AP to program MTRRs
//
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
//
// Wait for the signal from BSP to program MTRRs
//
WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
//
// Restore OS MTRRs
//
SmmCpuFeaturesReenableSmrr ();
MtrrSetAllMtrrs (&Mtrrs);
}
//
// Notify BSP the readiness of this AP to Reset states/semaphore for this processor
//
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
//
// Wait for the signal from BSP to Reset states/semaphore for this processor
//
WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
//
// Reset states/semaphore for this processor
//
*(mSmmMpSyncData->CpuData[CpuIndex].Present) = FALSE;
//
// Notify BSP the readiness of this AP to exit SMM
//