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framework.s65
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framework.s65
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;-------------------------------------------------------------------------
; RASTER FX FRAMEWORK
;-------------------------------------------------------------------------
;
; From the including file:
;
; To add stuff to zero page, put .fill directives in a '.section
; zp'...'.send zp' block. These values will automatically be zeroed on
; startup.
;
; To add code, put code in a '.section code'...'.send code' block.
;
; The following routines must be provided:
;
; 1. fx_init_1 - called once, with interrupts enabled and ZP cleared,
; before anything else happens.
;
; (If fx_init_1 changes mode, it must set the OS copy of the video ULA
; register to indicate whether it's a 1MHz or 2MHz mode - so change
; mode with VDU22 and/or use *FX154 to update the video ULA register.)
;
; 2. fx_init_2 - called once, roughly at start of frame, interrupts
; disabled, once things are set up
;
; 3. fx_draw - called every frame, so its first cycle is exactly at
; the top left of the visible frame
;
; 4. fx_update - called every frame to update stuff
;
; To adjust when fx_draw is called, set draw_timer_adjustment - units
; are microseconds. Positive values will cause fx_draw to be called
; earlier, so that the first useful write can line up with the start
; of the visible display.
;
;-------------------------------------------------------------------------
; OS defines
;-------------------------------------------------------------------------
osnewl=$ffe7
osfile = $FFDD
oswrch = $FFEE
osasci = $FFE3
osbyte = $FFF4
osword = $FFF1
osfind = $FFCE
osgbpb = $FFD1
osargs = $FFDA
oscli=$fff7
;-------------------------------------------------------------------------
; Key codes
key_space=$62
key_comma=$66
key_minus=$17
key_stop=$67
key_slash=$68
key_0=$27
key_1=$30
key_2=$31
key_3=$11
key_4=$12
key_5=$13
key_6=$34
key_7=$24
key_8=$15
key_9=$26
key_colon=$48
key_semicolon=$57
key_at=$47
key_a=$41
key_b=$64
key_c=$52
key_d=$32
key_e=$22
key_f=$43
key_g=$53
key_h=$54
key_i=$25
key_j=$45
key_k=$46
key_l=$56
key_m=$65
key_n=$55
key_o=$36
key_p=$37
key_q=$10
key_r=$33
key_s=$51
key_t=$23
key_u=$35
key_v=$63
key_w=$21
key_x=$42
key_y=$44
key_z=$61
key_left_square_bracket=$38
key_backslash=$78
key_right_square_bracket=$58
key_caret=$18
key_underline=$28
key_escape=$70
key_tab=$60
key_caps_lock=$40
key_ctrl=$1
key_shift_lock=$50
key_shift=$0
key_delete=$59
key_copy=$69
key_return=$49
key_up=$39
key_down=$29
key_left=$19
key_right=$79
key_f0=$20
key_f1=$71
key_f2=$72
key_f3=$73
key_f4=$14
key_f5=$74
key_f6=$75
key_f7=$16
key_f8=$76
key_f9=$77
;-------------------------------------------------------------------------
mode2_palette .function mode2_palette_index,mode2_palette_physical
.endf (mode2_palette_index<<4)|(mode2_palette_physical^7)
; this produces the left value
mode2_left .function mode2_left_index
.endf ((mode2_left_index&8)<<4)|((mode2_left_index&4)<<3)|((mode2_left_index&2)<<2)|((mode2_left_index&1)<<1)
mode2_right .function mode2_right_index
.endf mode2_left(mode2_right_index)>>1
mode2_value .function mode2_value_left,mode2_value_right
.endf mode2_left(mode2_value_left)|mode2_right(mode2_value_right)
;-------------------------------------------------------------------------
; this produces the left pixel
mode5_left .function mode5_3_index
.endf ((mode5_3_index&2)<<6)|((mode5_3_index&1)<<3)
mode5_value .function mode5_0,mode5_1,mode5_2,mode5_3
.endf (mode5_left(mode5_0)>>0)|(mode5_left(mode5_1)>>1)|(mode5_left(mode5_2)>>2)|(mode5_left(mode5_3)>>3)
;-------------------------------------------------------------------------
; http://6502.org/tutorials/65c02opcodes.html
nops: .macro ncycles
n:=\ncycles
.cerror n==1,"can't delay for just 1 cycle"
.if n%2==1
sta nops_tmp
n:=n-3
.endif
.rept n/128
jsr cycles_wait_128
n:=n-128
.next
.rept n/12
jsr cycles_wait_12
n:=n-12
.next
.rept n/2
nop
.next
.endm
crtc_addr .function addr
.cerror (addr&7)!=0,"invalid CRTC addr"
.endf addr>>3
; 16 cycles
; TODO - should be set_crtc
set_crtc: .macro r,v
lda #\r
sta $fe00
lda #\v
sta $fe01
.endm
; 6 cycles
set_mode2_palette: .macro index,colour
lda #mode2_palette(\index,\colour)
sta $fe21
.endm
;-------------------------------------------------------------------------
.weak
draw_timer_adjustment=0
start_address=$1900
max_end_address=$3000
show_cursor=false
.endweak
video_control=$fe20
video_palette=$fe21
acccon=$fe34
romsel=$fe30
; Exact time for a 50Hz frame less latch load time
FramePeriod = 312*64-2
; First timer value - times from vsync interrupt to wherever the
; fx_init_function should get called.
;
; This value is for the Mode 2 default CRTC values, with R5=0 and
; interlace off:
;
; 40 is the vblank length (312-272);
;
; 2 is the vblank period (the IRQ occurs on scanline 274);
;
; 7 can probably go away, but I haven't sat down and done that;
;
; 2 is the latch load time (???).
;
; (-2-7 puts the start of fx_init_function at the top left of the
; screen. Subtract more cycles to shift it further back.)
TimerValue = 40*64 - 2*64 - 2 - 7 - draw_timer_adjustment
; 40 lines for vblank
; 32 lines for vsync (vertical position = 35 / 39)
; interupt arrives 2 lines after vsync pulse
; 2 us for latch
; XX us to fire the timer before the start of the scanline so first colour set on column -1
; YY us for code that executes after timer interupt fires
;-------------------------------------------------------------------------
; ZERO PAGE
;-------------------------------------------------------------------------
*=$70
zp_start:
.dsection zp
.cerror *>=$9f,"ZP overflow"
zp_end:
.section zp
vsync_counter: .fill 2 ; counts up with each vsync
nops_tmp: .fill 1 ; may be overwritten by .nops macro
.send
;-------------------------------------------------------------------------
*=start_address
.dsection code
.cerror *>=max_end_address,"main RAM overflow"
;-------------------------------------------------------------------------
; Code entry
;-------------------------------------------------------------------------
.section code
main: .block
; Set interrupts
; Initalise system vars
ldx #zp_start
lda #0
-
sta 0,x
inx
cpx #zp_end
bne -
lda #144 ;*TV
ldx #255 ;R7+1 adjustment
ldy #1 ;interlace off
jsr osbyte
; Initialise system modules here!
; Load SIDEWAYS RAM modules here!
jsr fx_init_1
; get video ULA control register value
lda #$b8 ;AUG 193, MasRef D.2-56
ldx #0
ldy #255
jsr osbyte
txa
pha ;save video ULA control register value
.if !show_cursor
; Turn off cursor
.set_crtc 10,32
.endif
lda #19
jsr osbyte
sei ; disable interupts
lda #$7F ; A=01111111
sta $FE4E ; R14=Interrupt Enable (disable all interrupts)
sta $FE43 ; R3=Data Direction Register "A" (set
; keyboard data direction)
lda #$C2 ; A=11000010
sta $FE4E ; R14=Interrupt Enable (enable main_vsync
; and timer interrupt)
; http://www.retrosoftware.co.uk/wiki/index.php?title=Reading_the_keyboard_by_direct_hardware_access
lda #$0f
sta $fe42
lda #$03
sta $fe40
; DEMO START - from here on out there are no interrupts enabled!!
; sei
; jsr fx_kill_function
; Exact cycle VSYNC by Hexwab
.set_crtc 0,0
; DRAM refresh is inhibited in this state, so don't
; wait too long.
;
; The horizontal total register is 8 bits, so a delay
; of 256+ cycles is required.
jsr cycles_wait_256
lda #0
sta $fe00
ldx #63 ;appropriate R0 value for 1MHz modes
pla ;restore video ULA control register
;value
and #$10 ;Z=0 if 2MHz, Z=1 if 1MHz
beq + ;taken if 1MHz mode
ldx #127 ;appropriate R0 value for 2MHz modes
+
stx $fe01
lda #2
-
bit $FE4D
beq - ; wait for vsync
;now we're within 10 cycles of vsync having hit
;delay just less than one frame
syncloop:
sta $FE4D ; 4(stretched), ack vsync
;{ this takes (5*ycount+2+4)*xcount cycles
;x=55,y=142 -> 39902 cycles. one frame=39936
ldx #142 ;2
deloop:
ldy #55 ;2
innerloop:
dey ;2
bne innerloop ;3
; =152
dex ; 2
bne deloop ;3
;}
ldx #<TimerValue ; nop
ldy #>TimerValue ; nop
nop
nop
nop
nop
nop
nop
nop ; +16
bit $FE4D ;4(stretched)
bne syncloop ; +3
; 4+39902+16+4+3+3 = 39932
; ne means vsync has hit
; loop until it hasn't hit
;now we're synced to vsync
; Set up Timers
set_timers:
; Write T1 low now (the timer will not be written
; until you write the high byte)
; lda #<TimerValue
stx $FE44
; Get high byte ready so we can write it as quickly as
; possible at the right moment
; ldx #>TimerValue
sty $FE45 ; start T1 counting ; 4c +1/2c
; Latch T1 to interupt exactly every 50Hz frame
lda #<FramePeriod
sta $FE46
lda #>FramePeriod
sta $FE47
; Initialise FX modules here
call_init:
jsr fx_init_2
; We don't know how long the init took so resync to timer 1
lda #$42
sta $FE4D ; clear vsync $ timer 1 flags
; Wait for Timer1 at rasterline 0
lda #$40
-
bit $FE4D
beq -
sta $FE4D
; Now can enter main loop with enough time to do work
; Update typically happens during vblank so wait 255 lines
; But don't forget that the loop also takes time!!
ldx #245
-
jsr cycles_wait_128
dex
bne -
; MAIN LOOP
main_loop:
; Do useful work during vblank (vsync will occur at
; some point)
inc vsync_counter
bne +
inc vsync_counter+1
+
; Service any system modules here!
; ; Check for Escape key
; lda #$79
; ldx #($70 ^ $80)
; jsr osbyte
; stx escape_pressed
; FX update callback here!
call_update:
jsr fx_update
; Wait for first scanline
; Wait for T1<256
-
lda $fe45
bne -
.page
-
ldx $fe44
cpx #19 ;+2 2
bcs - ;+2 4
lda dejitter_offsets,x ;+4 8
sta dejitter_jmp+1 ;+4 12
dejitter_jmp:
jmp dejitter_jmp&$ff00 ;+3 18
;jsr = +6 24
case_18:
nop
case_17:
nop
case_16:
nop
case_15:
nop
case_14:
nop
case_13:
nop
case_12:
nop
case_11:
nop
case_10:
nop
no_delay:
call_draw:
jsr fx_draw
jmp main_loop
dejitter: .macro dest
.byte \dest&$ff
.endm
dejitter_offsets:
.rept 10
.dejitter no_delay
.next
.dejitter case_10
.dejitter case_11
.dejitter case_12
.dejitter case_13
.dejitter case_14
.dejitter case_15
.dejitter case_16
.dejitter case_17
.dejitter case_18
.endp
.bend
;-------------------------------------------------------------------------
; HELPER FUNCTIONS
;-------------------------------------------------------------------------
cycles_wait_32768:
jsr cycles_wait_16384
cycles_wait_16384:
jsr cycles_wait_8192
cycles_wait_8192:
jsr cycles_wait_4096
cycles_wait_4096:
jsr cycles_wait_2048
cycles_wait_2048:
jsr cycles_wait_1024
cycles_wait_1024:
jsr cycles_wait_512
cycles_wait_512:
jsr cycles_wait_256
cycles_wait_256:
jsr cycles_wait_128
cycles_wait_128: ; JSR to get here takes 6c
.nops 116
cycles_wait_12:
rts
print_string: .proc
pla
sta rd+1
pla
sta rd+2
-
rd:
.if (*&$ff)==$fe
nop
.endif
lda $ffff
inc rd+1
bne +
inc rd+2
+
cmp #255
beq +
jsr oswrch
jmp -
+
jmp (rd+1)
.pend
load_mode2_screen: .proc
lda #22
jsr oswrch
lda #2
jsr oswrch
ldx #<load_screen
ldy >#load_screen
jsr oscli
rts
load_screen:
.text "LOAD $.SCREEN",13
.pend
;-------------------------------------------------------------------------
.send code