Makefile.udiv17

SHELL = /bin/bash

SIM_DIR = sim

VERILATOR = verilator

VERILATOR_OPTS = \
	-Wall \
	-Wno-WIDTH \
	-Wno-UNUSED \
	-Wno-BLKSEQ \
	--cc \
	+1364-2001ext+v \
	-Wno-fatal \
	--Mdir sim \
	--trace \

VERILATOR_MAKE_OPTS = OPT_FAST="-O3"

DESIGN_SRCS = \
div17.v \
vscale_mul_div.v \

VERILATOR_CPP_TB = udiv17_tb.cpp

default: $(SIM_DIR)/Vdiv17

sim: $(SIM_DIR)/Vdiv17

$(SIM_DIR)/Vdiv17: $(DESIGN_SRCS) $(VERILATOR_CPP_TB)
	$(VERILATOR) $(VERILATOR_OPTS) $(DESIGN_SRCS) --exe ../$(VERILATOR_CPP_TB)
	cd sim; make $(VERILATOR_MAKE_OPTS) -f Vdiv17.mk Vdiv17__ALL.a
	cd sim; make $(VERILATOR_MAKE_OPTS) -f Vdiv17.mk Vdiv17

clean:
	rm -rf sim/ tmp.vcd

.PHONY: