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chapter-instr-close.tex
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chapter-instr-close.tex
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\chapter{Instructions up Close}
\label{instruction_details}
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\input{defines-instr-close.tex}
The following pages describe all instructions in detail. Alphabetical order is used as much as possible, but some deviations were made to better fit to pages. Each instruction includes:
\begin{itemize}
\setlength\itemsep{1pt}
\item Mnemonic
\item Symbolic operation for quick info on what instruction does
\item All variants (where applicable)
\item Description with further details
\item Effects on flags
\item Timing table with machine cycles, T states and time required for execution on different CPU speeds
\end{itemize}
Where possible, multiple variants of same instruction are grouped together and where multiple timings are possible, timing table is sorted from quickest to slowest.
\pagebreak
\thispagestyle{plain} % use toc style without headers for this explanation page, it better matches chapter start page
\subsubsection{Flags}
\newcommand{\DetailsFlagTableList}[1]{
\vspace*{-2ex}
\setlist{leftmargin=1em,after=\vspace{-2ex}}
\begin{itemize}
\setlength\itemsep{-4pt}
#1
\end{itemize}
}
\newcommand{\DetailsFlagTableParagraph}{\vspace{1ex}}
{
\renewcommand{\arraystretch}{1.5}
\begin{tabularx}{\linewidth}{cX}
\FlagSF{} &
\textbf{Sign Flag} is set to twos-complement of the most-significant bit (bit 7) of the result of an instruction. If the result is positive (bit 7 is {\tt 0}), \FlagSF{} is set, and if the result is negative (bit 7 is {\tt 1}), \FlagSF{} is reset. This leaves bits 0-6 to represent the value. Positive numbers range from {\tt 0} to {\tt 127} and negative from {\tt -1} to {\tt -128}.
\\
\FlagZF{} &
\textbf{Zero Flag} depends on whether the result of an instruction is {\tt 0}. \FlagZF{} is set if the result if {\tt 0} and reset otherwise.
\\
\FlagHF{} &
\textbf{Half Carry Flag} represents a carry or borrow status between bits 3 and 4 of an 8-bit arithmetic operation (bits 11 and 12 for 16-bit operations). Set if:
\DetailsFlagTableList{
\item A carry from bit 3 to bit 4 occurs during addition (bit 11 to 12 for 16-bit operations)
\item A borrow from bit 4 occurs during subtraction (from bit 12 for 16-bit operations)
}
\\
\FlagPV{} &
\textbf{Parity/Overflow Flag} value depends on the type of the operation.
\DetailsFlagTableParagraph
For arithmetic operations, \FlagPV{} indicates an overflow. The flag is set when the sign of the result is different from the sign of the operands:
\DetailsFlagTableList{
\item all operands are positive but the result is negative or
\item all operands are negative but the result is positive
}
\DetailsFlagTableParagraph
For logical and rotate operations, \FlagPV{} indicates the parity of the result. The number of set bits in the result are counted. If the total is an even value, \FlagPV{} is set. If the total is odd, \FlagPV{} is reset.
\\
\FlagNF{} &
\textbf{Add/Subtract Flag} is used primarily for {\tt DAA} instruction to distinguish between add and subtract operations. But other instructions may also affect it as described in the following pages.
\\
\textbf{CF} &
\textbf{Carry Flag} represents a carry or borrow status for arithmetic operations. \textbf{CF} is set if add instruction generates a carry, or subtract generates a borrow.
\DetailsFlagTableParagraph
For rotate and shift instructions, \textbf{CF} is used:
\DetailsFlagTableList{
\item as a link between least-significat and most significant bit for {\tt RLA}, {\tt RL}, {\tt RRA} and {\tt RR}
\item contains the value shifted out of bit 7 for {\tt RLC}, {\tt RLCA} and {\tt SLA}
\item contains the value shifted out of bit 0 for {\tt RRC}, {\tt RRCA}, {\tt SRA} and {\tt SRL}
}
\DetailsFlagTableParagraph
Finally, some instructions directly affect the value of \textbf{CF}:
\DetailsFlagTableList{
\item reset with {\tt AND}, {\tt OR} and {\tt XOR}
\item set with {\tt SCF}
\item completed with {\tt CCF}
}
\\
\end{tabularx}
}
\subsubsection{Effects}
\begin{tabular}{cl}
{\tt 0} & Flag is set to {\tt 0} \\
{\tt 1} & Flag is set to {\tt 1} \\
{\tt \FS} & Flag is modified according to operation \\
{\tt \FN} & Flag is not affected \\
{\tt \FU} & Effect on flag is unpredictable \\
{\tt \FX} & Special case, see notes below effects table \\
\DetailParityOverflow{v} & P/V flag is used as overflow \\
\DetailParityOverflow{p} & P/V flag is used as parity \\
\DetailParityOverflow{} & P/V is undefined or indicates other result \\
\end{tabular}
\subsubsection{Abbreviations}
\begin{tabularx}{\textwidth}{lX}
{\tt r} &
8-bit register {\tt A}-{\tt L} \\
{\tt n} &
8-bit immediate value \\
{\tt rr} &
16-bit register pair {\tt AF}, {\tt BC}, {\tt DE}, {\tt HL}, {\tt IX}, {\tt IY}, {\tt SP} (note in some cases particular register pairs may use different timing from the rest; if so, those will be explicitly indicated in their own line; {\tt rr} may still be used, though in those cases it will cover the remaining registers only) \\
{\tt nn} &
16-bit immediate value \\
{\tt s} &
Placeholder for argument when multiple variants are possible \\
{\tt d} &
If instruction takes 2 operands, {\tt d} indicates destination and {\tt s} source \\
\UNDOC & Indicates undocumented instruction \\
\ZXN & Indicates ZX Spectrum Next extended instruction \\
\end{tabularx}
\pagebreak
\IntentionallyEmpty
\pagebreak
\begin{basedescript}{
% setup basedescript styling for labels
\desclabelstyle{\multilinelabel}
\desclabelwidth{3cm}}
% setup spacing between items
\setlength\itemsep{1.5em}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{ADC}{d,s}
{\IH{AD}d with \IH{C}arry}
{\SymADC{d}{s}}
\begin{DetailVariants}[p{1.9cm}p{1.9cm}Xp{2.8cm}p{2.4cm}]
\textnormal{8 bit} & \textnormal{8 bit} & \textnormal{8 bit} & \textnormal{8 bit} & \textnormal{16 bit} \\
ADC A,A & ADC A,E & ADC A,(HL) & ADC A,IXH\UNDOC & ADC HL,BC \\
ADC A,B & ADC A,H & ADC A,(IX+d) & ADC A,IXL\UNDOC & ADC HL,DE \\
ADC A,C & ADC A,L & ADC A,(IY+d) & ADC A,IYH\UNDOC & ADC HL,HL \\
ADC A,D & ADC A,n & & ADC A,IYL\UNDOC & ADC HL,SP \\
\end{DetailVariants}
Adds source operand {\tt s} or contents of the memory location addressed by {\tt s} and value of carry flag to destination {\tt d}. Result is then stored to destination {\tt d}.
\begin{DetailEffects}[v]
\FlagsADCr[8-bit]
\FlagsADCrr[16-bit]
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagHF{\DetailFlagResultHalfCarry}*
\DetailFlagPV{\DetailFlagResultOverflow}*
\DetailFlagCF{\DetailFlagResultCarry}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[A,r]{1}{4}
\DetailTime[A,n]{2}{7}
\DetailTime[A,(HL)]{2}{7}
\DetailTime[HL,rr]{4}{15}
\DetailTime[A,(IX+d)]{5}{19}
\DetailTime[A,(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{ADD}{d,s}
{\IH{ADD}}
{\SymADD{d}{s}}
\begin{DetailVariants}[p{1.9cm}Xp{2.3cm}p{2.3cm}p{2.4cm}]
\textnormal{8-bit} & \textnormal{8-bit} & \textnormal{16-bit} & \textnormal{16-bit} & \textnormal{ZX Next} \\
ADD A,A & ADD A,(HL) & ADD IX,BC & ADD HL,BC & ADD BC,A\ZXN \\
ADD A,B & ADD A,(IX+d) & ADD IX,DE & ADD HL,DE & ADD DE,A\ZXN \\
ADD A,C & ADD A,(IY+d) & ADD IX,IX & ADD HL,HL & ADD HL,A\ZXN \\
ADD A,D & ADD A,IXH\UNDOC & ADD IX,SP & ADD HL,SP & ADD BE,nn\ZXN \\
ADD A,E & ADD A,IXL\UNDOC & ADD IY,BC & & ADD DE,nn\ZXN \\
ADD A,H & ADD A,IYH\UNDOC & ADD IY,DE & & ADD HL,nn\ZXN \\
ADD A,L & ADD A,IYL\UNDOC & ADD IY,IY \\
ADD A,n & & ADD IY,SP \\
\end{DetailVariants}
Similar to {\tt ADC} except carry flag is not used in calculation: adds operand {\tt s} or contents of the memory location addressed by {\tt s} to destination {\tt d}. Result is then stored to destination {\tt d}.
ZX Next Extended instructions for adding {\tt A} to 16-bit register pair, zero extend {\tt A} to 16-bits.
\begin{DetailEffects}[v]
\FlagsADDr[8-bit]
\FlagsADDrr[16-bit]
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[8-bit only, set if:]{\DetailFlagResultSign}
\DetailFlagZF[8-bit only, set if:]{\DetailFlagResultZero}
\DetailFlagHF{\DetailFlagResultHalfCarry*}*
\DetailFlagPV[8-bit only, set if:]{\DetailFlagResultOverflow}*
\DetailFlagCF{\DetailFlagResultCarry*}
\end{DetailEffectsFlags}
\begin{DetailEffects}
\FlagsADDrra[\tt ADD rr,A\ZXN]
\FlagsADDrrnn[\tt ADD rr,nn\ZXN]
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[A,r]{1}{4}
\DetailTime[A,n]{2}{7}
\DetailTime[A,(HL)]{2}{7}
\DetailTime[rr,A\ZXN]{2}{8}
\DetailTime[HL,rr]{3}{11}
\DetailTime[IX,rr]{4}{15}
\DetailTime[IY,rr]{4}{15}
\DetailTime[rr,nn\ZXN]{4}{16}
\DetailTime[A,(IX+d)]{5}{19}
\DetailTime[A,(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{AND}{s}
{bitwise \IH{AND}}
{\SymAND{s}}
\begin{DetailVariants}[4]
AND A\\
AND B\\
AND C\\
AND D
\columnbreak
AND E\\
AND H\\
AND L\\
AND n
\columnbreak
AND (HL)\\
AND (IX+d)\\
AND (IY+d)
\columnbreak
AND IXH\UNDOC\\
AND IXL\UNDOC\\
AND IYH\UNDOC\\
AND IYL\UNDOC
\end{DetailVariants}
\begin{tabularx}{\linewidth}{@{}Xl}
Performs bitwise AND between accumulator {\tt A} and the given operand. The result is then stored back to the accumulator. Individual bits are AND'ed as shown on the right:
&
\begin{tabular}[t]{cc|c}
{\tt A} & {\tt s} & Result \\
\hline
{\tt 0} & {\tt 0} & {\tt 0} \\
{\tt 0} & {\tt 1} & {\tt 0} \\
{\tt 1} & {\tt 0} & {\tt 0} \\
{\tt 1} & {\tt 1} & {\tt 1} \\
\end{tabular}
\\
\end{tabularx}
\begin{DetailEffects}[p]
\FlagsANDr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{1}{4}
\DetailTime[n]{2}{7}
\DetailTime[(HL)]{2}{7}
\DetailTime[(IX+d)]{5}{19}
\DetailTime[(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BIT}{b,s}
{test \IH{BIT}}
{\SymBIT{s}}
\begin{DetailVariants}
BIT b,A\\
BIT b,B\\
BIT b,C\\
BIT b,D
\columnbreak
BIT b,E\\
BIT b,H\\
BIT b,L
\columnbreak
BIT b,(HL)\\
BIT b,(IX+d)\\
BIT b,(IY+d)
\end{DetailVariants}
Tests specified bit {\tt b} ({\tt 0-7}) of the given register {\tt s} or contents of memory addressed by {\tt s} and sets zero flag according to result; if bit was 1, \FlagZF{} is 0 and vice versa.
\begin{DetailEffects}
\FlagsBITr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagZF{bit {\tt b} of the given source argument is {\tt 0}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[b,r]{2}{8}
\DetailTime[b,(HL)]{3}{12}
\DetailTime[b,(IX+d)]{5}{20}
\DetailTime[b,(IY+d)]{5}{20}
\end{DetailTiming}
\end{DetailItem}
% these instructions should be here in alphabetical order, but I want them to be placed on the same page spread so reader can check the differences easily
\DetailItemsSeePageReference{BRLC, BSLA, BSRA, BSRF, BSRL}{See pages \DetailItemPageRef{BRLC} and \DetailItemPageRef{BSRL}}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CALL}{nn}
{\IH{CALL} subroutine}
{\SymCALL{nn}}
Pushes program counter {\tt PC} to stack and calls subroutine at the given location {\tt nn} by changing {\tt PC} to point to address {\tt nn}.
\begin{DetailEffects}
\FlagsCALLnn
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{5}{17}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CALL c,nn}{}
{\IH{CALL} subroutine conditionally}
{\SymCALLc{nn}}
\vspace{1ex} % we need some vertical space to achieve same separation as multicols
\begin{tabular}{@{}llcll}
{\tt CALL C,nn} & calls if \FlagCF{} is set & &
{\tt CALL M,nn} & calls if \FlagSF{} is set\\
{\tt CALL NC,nn} & calls if \FlagCF{} is reset & &
{\tt CALL P,nn} & calls if \FlagSF{} is reset\\
{\tt CALL Z,nn} & calls if \FlagZF{} is set & &
{\tt CALL PE,nn} & calls if \FlagPV{} is set\\
{\tt CALL NZ,nn} & calls if \FlagZF{} is reset & &
{\tt CALL PO,nn} & calls if \FlagPV{} is reset\\
\end{tabular}
If the given condition is met, {\tt CALL nn} is performed, as described above.
\begin{DetailEffects}
\FlagsCALLccnn
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[c\normalfont{=false}]{3}{10}
\DetailTime[c\normalfont{=true}]{5}{17}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BRLC}{DE,B\ZXN}
{\IH{B}arrel \IH{R}otate \IH{L}eft \IH{C}ircular}
{\SymBRLC}
Rotates value in register pair {\tt DE} left for the amount given in bits 3-0 (low nibble) of register {\tt B}. To rotate right, use formula: {\tt B=16-places}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBRLC
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BSLA}{DE,B\ZXN}
{\IH{B}arrel \IH{S}hift \IH{L}eft \IH{A}rithmetic}
{\SymBSLA}
Performs shift left of the value in register pair {\tt DE} for the amount given in lower 5 bits of register {\tt B}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBSLA
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BSRA}{DE,B\ZXN}
{\IH{B}arrel \IH{S}hift \IH{R}ight \IH{A}rithmetic}
{\SymBSRA}
Performs arithmetical shift right of the value in register pair {\tt DE} for the amount given in lower 5 bits of register {\tt B}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBSRA
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BSRF}{DE,B\ZXN}
{\IH{B}arrel \IH{S}hift \IH{R}ight \IH{F}ill-one}
{\SymBSRF}
Performs fill-one-way shift right of the value in register pair {\tt DE} for the amount given in lower 5 bits of register {\tt B}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBSRF
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BSRL}{DE,B\ZXN}
{\IH{B}arrel \IH{S}hift \IH{R}ight \IH{L}ogical}
{\SymBSRL}
Performs logical shift right of the value in register pair {\tt DE} for the amount given in lower 5 bits of register {\tt B}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBSRL
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
% CALL instructions should be here in alphabetical order, but I placed them before B*** above so they can be in the same page spread
\DetailItemSeePageReference{CALL}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CCF}{}
{\IH{C}omplement \IH{C}arry \IH{F}lag}
{\SymCCF}
Complements (inverts) carry flag \FlagCF{}; if \FlagCF{} was {\tt 0} it's now {\tt 1} and vice versa. Previous value of \FlagCF{} is copied to \FlagHF{}.
\begin{DetailEffects}
\FlagsCCF
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagHF[]{Documentation says original value of \FlagCF{} is copied to \FlagHF{}, however under my tests \FlagHF{} remained unchanged}
\DetailFlagCF[]{if \FlagCF{} was {\tt 0} it's now {\tt 1} and vice versa}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CP}{s}
{\IH{C}om\IH{P}are}
{\SymCP{s}}
\begin{DetailVariants}[4]
CP A\\
CP B\\
CP C\\
CP D
\columnbreak
CP E\\
CP H\\
CP L\\
CP n
\columnbreak
CP (HL)\\
CP (IX+d)\\
CP (IY+d)
\columnbreak
CP IXH\UNDOC\\
CP IXL\UNDOC\\
CP IYH\UNDOC\\
CP IYL\UNDOC
\end{DetailVariants}
Operand {\tt s} or content of the memory location addressed by {\tt s} is subtracted from accumulator {\tt A}. Status flags are updated according to the result, but the result is then discarded (value of {\tt A} is not changed).
\begin{DetailEffects}[v]
\FlagsCPr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagHF{\DetailFlagResultHalfBorrow}*
\DetailFlagPV{
\DetailFlagsList{
\item {\tt A} and {\tt s} positive and {\tt A-s} result negative
\item {\tt A} and {\tt s} negative and {\tt A-s} result positve
}
\DetailFlagResultOverflowListBottomSpacing % we don't want additional space below the table, otherwise next item would have larger gap
}
\end{DetailEffectsFlags}
Other flags are set like this when {\tt A} is greater than, equal or less than {\tt s}:
\begin{DetailEffects}[v][]
\Flags[A$>$s]{0}{0}{\FS}{\FS}{1}{0}
\Flags[A$=$s]{0}{1}{\FS}{\FS}{1}{0}
\Flags[A$<$s]{1}{0}{\FS}{\FS}{1}{1}
\end{DetailEffects}
With this in mind, we can derive the programs for common comparisons:
\newcommand{\CPExampleTitle}[1]{{\tt #1}\vspace{-1.5ex}}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A=s}
\begin{tcblisting}{right skip=1em}
CP s
JP Z, true ; A=s?
false: ; A!=s
true: ; A=s
\end{tcblisting}
\CPExampleTitle{A$\neq$s}
\begin{tcblisting}{}
CP s
JP NZ, true ; A!=s?
false: ; A=s
true: ; A!=s
\end{tcblisting}
\end{multicols}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A$\leqslant$s}
\begin{tcblisting}{right skip=1em}
CP s
JP M, true ; A<s?
JP Z, true ; A=s?
false: ; A>s
true: ; A<=s
\end{tcblisting}
\columnbreak
\CPExampleTitle{A<s}
\begin{tcblisting}{}
CP s
JP M, true ; A<s?
false: ; A>=s
true: ; A<s
\end{tcblisting}
\end{multicols}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A$\geqslant$s}
\begin{tcblisting}{right skip=1em}
CP s
JP M, false ; A<s?
true: ; A>=s
false: ; A<s
\end{tcblisting}
\columnbreak
\CPExampleTitle{A>s}
\begin{tcblisting}{}
CP s
JP M, false ; A<s?
JP Z, false ; A=s?
true: ; A>s
false: ; A<=s
\end{tcblisting}
\end{multicols}
\DetailNote[-1ex]{
Note: the examples use two labels to emphasize both results. But only one is needed. Furthermore, depending on the actual needs, the programs can also use no label at all. For example, we can use {\tt RET} instead of {\tt JP} when used within a subroutine, and the desired outcome is to return if the condition is not met:
}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A=s}
\begin{tcblisting}{right skip=1em}
CP s
RET NZ ; A!=s?
; A=s
\end{tcblisting}
\CPExampleTitle{A$\neq$s}
\begin{tcblisting}{}
CP s
RET Z ; A=s?
; A!=s
\end{tcblisting}
\end{multicols}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A$\leqslant$s}
\begin{tcblisting}{right skip=1em}
CP s
JP M, true ; A<s?
JP Z, true ; A=s?
RET ; A>s
true: ; A<=s
\end{tcblisting}
\columnbreak
\CPExampleTitle{A<s}
\begin{tcblisting}{}
CP s
RET P ; A>=s?
; A<s
\end{tcblisting}
\end{multicols}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A$\geqslant$s}
\begin{tcblisting}{right skip=1em}
CP s
RET M ; A<s?
; A>=s
\end{tcblisting}
\CPExampleTitle{A>s}
\begin{tcblisting}{}
CP s
RET M ; A<s?
RET Z ; A=s?
; A>s
\end{tcblisting}
\end{multicols}
\DetailNote[-1ex]{
Note: some of the comparisons are reversed. And {\tt A$\leqslant$s} still requires a label because the condition is true if either \FlagSF{} or \FlagZF{} is set.
}
\DetailNote{
Note: I opted to use \FlagSF{} for some of the comparisons. It makes more sense to me this way. But you can just as well use \FlagCF{} instead. As evident from the table on the previous page, both flags are updated the same way, so you could use {\tt JP C} or {\tt RET C} instead of {\tt M} and {\tt JP NZ} or {\tt RET NZ} instead of {\tt P}. This is due to {\tt CP} performing a subtraction {\tt A-s} internally. So when {\tt s} is greater than {\tt A}, the result of the subtraction is negative, meaning the sign flag is set. At the same time a borrow is needed, so the carry is set too. I thought it's worth mentioning since you may find examples using the carry flag elsewhere and wonder why.
}
\vspace{2ex} % some vertical gap between notes and timings
\begin{DetailTiming}
\DetailTime[r]{1}{4}
\DetailTime[n]{2}{7}
\DetailTime[(HL)]{2}{7}
\DetailTime[(IX+d)]{5}{19}
\DetailTime[(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
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\begin{DetailItem}{CPD}{}
{\IH{C}om\IH{P}are and \IH{D}ecrement}
{\SymCPD}
Subtracts contents of memory location addressed by {\tt HL} register pair from accumulator {\tt A}. Result is then discarded. Afterwards both {\tt HL} and {\tt BC} are decremented.
\begin{DetailEffects}
\FlagsCPD
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{{\tt A<(HL)} before {\tt HL} is decremented}
\DetailFlagZF{{\tt A=(HL)} before {\tt HL} is decremented}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CPDR}{}
{\IH{C}om\IH{P}are and \IH{D}ecrement \IH{R}epeated}
{\SymCPDR}
Repeats {\tt CPD} until either {\tt A=(HL)} or {\tt BC=0}. If {\tt BC} is set to {\tt 0} before instruction execution, it loops through 64KB if no match is found. See {\tt CPIR} for example.
\begin{DetailEffects}
\FlagsCPDR
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{{\tt A<(HL)} before {\tt HL} is decremented}
\DetailFlagZF{{\tt A=(HL)} before {\tt HL} is decremented}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTimeRegular[{\tt BC}=0 or {\tt A}={\tt (HL)}]{4}{16}
\DetailTimeRegular[{\tt BC}$\neq$0 and {\tt A}$\neq${\tt (HL)}]{5}{21}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CPI}{}
{\IH{C}om\IH{P}are and \IH{I}ncrement}
{\SymCPI}
Subtracts contents of memory location addressed by {\tt HL} register pair from accumulator {\tt A}. Result is then discarded. Afterwards {\tt HL} is incremented and {\tt BC} decremented.
\begin{DetailEffects}
\FlagsCPI
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{{\tt A<(HL)} before {\tt HL} is decremented}
\DetailFlagZF{{\tt A=(HL)} before {\tt HL} is decremented}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CPIR}{}
{\IH{C}om\IH{P}are and \IH{D}ecrement \IH{R}epeated}
{\SymCPIR}
Repeats {\tt CPI} until either {\tt A=(HL)} or {\tt BC=0}. If {\tt BC} is set to {\tt 0} before instruction execution, it loops through 64KB if no match is found.
Example, searching for {\tt \$AB} in memory from \MemAddr{0000}-\MemAddr{999}:
\begin{multicols}{2}
{\tt CPIR} = finding first occurrence:
\begin{tcblisting}{right skip=1em}
LD HL, &0000
LD BC, &0999
LD A, &AB
CPIR
\end{tcblisting}
{\tt CPDR} = finding last occurrence:
\begin{tcblisting}{}
LD HL, &0999
LD BC, &0999
LD A, &AB
CPDR
\end{tcblisting}
\end{multicols}
\begin{DetailEffects}
\FlagsCPIR
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{{\tt A<(HL)} before {\tt HL} is decremented}
\DetailFlagZF{{\tt A=(HL)} before {\tt HL} is decremented}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTimeRegular[{\tt BC}=0 or {\tt A}={\tt (HL)}]{4}{16}
\DetailTimeRegular[{\tt BC}$\neq$0 and {\tt A}$\neq${\tt (HL)}]{5}{21}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
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%----------------------------------------------------------------------------------------------------------------------
% by moving CPL to next page, we can have DAA fit the whole of the page. Otherwise last part (timing) doesn't fit the same page (it's still in the same spread, but this way it's nicer)
\DetailItemsSeePageReference{CPL}{See next page}
\begin{DetailItem}{DAA}{}
{\IH{D}ecimal \IH{A}djust \IH{A}ccumulator}
{}
Updates accumulator {\tt A} for BCD correction after arithmetic operations using the following algorithm:
\begin{enumerate}
\item The least significant 4 bits of accumulator {\tt A} (low nibble) are checked first. If they contain invalid BCD number (greater than 9), or \FlagHF{} is set, the value of {\tt A} is adjusted based on the value of \FlagNF{}: if it's reset, {\tt \$06} is added to {\tt A}, if set, {\tt \$06} is removed from {\tt A}.
\item Then 4 most significant bits of accumulator {\tt A} (high nibble) are checked in a similar fashion. If they contain invalid BCD number, or \textbf{CF} is set, the value of {\tt A} is adjusted: if \FlagNF{} is not set, {\tt \$60} is added to {\tt A}, if \FlagNF{} is set, {\tt \$60} is removed from {\tt A}.
\item Finally flags are changed accordingly, as described below.
\end{enumerate}
% Symbolically, the algorithm could be expressed as:
% {
% \tt \small
% if (A$\wedge$\$0F>\$09)$\vee$(HF=1):\\
% \hspace*{1em}if NF=0:~A$\leftarrow$A+\$06~else:~A$\leftarrow$A-\$06\\
% if (A$\wedge$\$F0>\$90)$\vee$(CF=1):\\
% \hspace*{1em}if NF=0:~A$\leftarrow$A+\$60~else:~A$\leftarrow$A-\$60\\
% }
\begin{DetailEffects}[p]
\FlagsDAA
\end{DetailEffects}
\newcommand{\DAAIn}[1]{#1}
\newcommand{\DAAOut}[1]{\RArrow{6pt}#1}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign[A] after operation}