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cs43130.c
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cs43130.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* cs43130.c -- CS43130 ALSA Soc Audio driver
*
* Copyright 2017 Cirrus Logic, Inc.
*
* Authors: Li Xu <li.xu@cirrus.com>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <linux/of_gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/of_irq.h>
#include <linux/completion.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <sound/jack.h>
#include "cs43130.h"
#include "cirrus_legacy.h"
static const struct reg_default cs43130_reg_defaults[] = {
{CS43130_SYS_CLK_CTL_1, 0x06},
{CS43130_SP_SRATE, 0x01},
{CS43130_SP_BITSIZE, 0x05},
{CS43130_PAD_INT_CFG, 0x03},
{CS43130_PWDN_CTL, 0xFE},
{CS43130_CRYSTAL_SET, 0x04},
{CS43130_PLL_SET_1, 0x00},
{CS43130_PLL_SET_2, 0x00},
{CS43130_PLL_SET_3, 0x00},
{CS43130_PLL_SET_4, 0x00},
{CS43130_PLL_SET_5, 0x40},
{CS43130_PLL_SET_6, 0x10},
{CS43130_PLL_SET_7, 0x80},
{CS43130_PLL_SET_8, 0x03},
{CS43130_PLL_SET_9, 0x02},
{CS43130_PLL_SET_10, 0x02},
{CS43130_CLKOUT_CTL, 0x00},
{CS43130_ASP_NUM_1, 0x01},
{CS43130_ASP_NUM_2, 0x00},
{CS43130_ASP_DEN_1, 0x08},
{CS43130_ASP_DEN_2, 0x00},
{CS43130_ASP_LRCK_HI_TIME_1, 0x1F},
{CS43130_ASP_LRCK_HI_TIME_2, 0x00},
{CS43130_ASP_LRCK_PERIOD_1, 0x3F},
{CS43130_ASP_LRCK_PERIOD_2, 0x00},
{CS43130_ASP_CLOCK_CONF, 0x0C},
{CS43130_ASP_FRAME_CONF, 0x0A},
{CS43130_XSP_NUM_1, 0x01},
{CS43130_XSP_NUM_2, 0x00},
{CS43130_XSP_DEN_1, 0x02},
{CS43130_XSP_DEN_2, 0x00},
{CS43130_XSP_LRCK_HI_TIME_1, 0x1F},
{CS43130_XSP_LRCK_HI_TIME_2, 0x00},
{CS43130_XSP_LRCK_PERIOD_1, 0x3F},
{CS43130_XSP_LRCK_PERIOD_2, 0x00},
{CS43130_XSP_CLOCK_CONF, 0x0C},
{CS43130_XSP_FRAME_CONF, 0x0A},
{CS43130_ASP_CH_1_LOC, 0x00},
{CS43130_ASP_CH_2_LOC, 0x00},
{CS43130_ASP_CH_1_SZ_EN, 0x06},
{CS43130_ASP_CH_2_SZ_EN, 0x0E},
{CS43130_XSP_CH_1_LOC, 0x00},
{CS43130_XSP_CH_2_LOC, 0x00},
{CS43130_XSP_CH_1_SZ_EN, 0x06},
{CS43130_XSP_CH_2_SZ_EN, 0x0E},
{CS43130_DSD_VOL_B, 0x78},
{CS43130_DSD_VOL_A, 0x78},
{CS43130_DSD_PATH_CTL_1, 0xA8},
{CS43130_DSD_INT_CFG, 0x00},
{CS43130_DSD_PATH_CTL_2, 0x02},
{CS43130_DSD_PCM_MIX_CTL, 0x00},
{CS43130_DSD_PATH_CTL_3, 0x40},
{CS43130_HP_OUT_CTL_1, 0x30},
{CS43130_PCM_FILT_OPT, 0x02},
{CS43130_PCM_VOL_B, 0x78},
{CS43130_PCM_VOL_A, 0x78},
{CS43130_PCM_PATH_CTL_1, 0xA8},
{CS43130_PCM_PATH_CTL_2, 0x00},
{CS43130_CLASS_H_CTL, 0x1E},
{CS43130_HP_DETECT, 0x04},
{CS43130_HP_LOAD_1, 0x00},
{CS43130_HP_MEAS_LOAD_1, 0x00},
{CS43130_HP_MEAS_LOAD_2, 0x00},
{CS43130_INT_MASK_1, 0xFF},
{CS43130_INT_MASK_2, 0xFF},
{CS43130_INT_MASK_3, 0xFF},
{CS43130_INT_MASK_4, 0xFF},
{CS43130_INT_MASK_5, 0xFF},
};
static bool cs43130_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
case CS43130_HP_DC_STAT_1 ... CS43130_HP_DC_STAT_2:
case CS43130_HP_AC_STAT_1 ... CS43130_HP_AC_STAT_2:
return true;
default:
return false;
}
}
static bool cs43130_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1:
case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG:
case CS43130_PWDN_CTL:
case CS43130_CRYSTAL_SET:
case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5:
case CS43130_PLL_SET_6:
case CS43130_PLL_SET_7:
case CS43130_PLL_SET_8:
case CS43130_PLL_SET_9:
case CS43130_PLL_SET_10:
case CS43130_CLKOUT_CTL:
case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF:
case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF:
case CS43130_ASP_CH_1_LOC:
case CS43130_ASP_CH_2_LOC:
case CS43130_ASP_CH_1_SZ_EN:
case CS43130_ASP_CH_2_SZ_EN:
case CS43130_XSP_CH_1_LOC:
case CS43130_XSP_CH_2_LOC:
case CS43130_XSP_CH_1_SZ_EN:
case CS43130_XSP_CH_2_SZ_EN:
case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3:
case CS43130_HP_OUT_CTL_1:
case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2:
case CS43130_CLASS_H_CTL:
case CS43130_HP_DETECT:
case CS43130_HP_STATUS:
case CS43130_HP_LOAD_1:
case CS43130_HP_MEAS_LOAD_1:
case CS43130_HP_MEAS_LOAD_2:
case CS43130_HP_DC_STAT_1:
case CS43130_HP_DC_STAT_2:
case CS43130_HP_AC_STAT_1:
case CS43130_HP_AC_STAT_2:
case CS43130_HP_LOAD_STAT:
case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5:
return true;
default:
return false;
}
}
static bool cs43130_precious_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
return true;
default:
return false;
}
}
struct cs43130_pll_params {
unsigned int pll_in;
u8 sclk_prediv;
u8 pll_div_int;
u32 pll_div_frac;
u8 pll_mode;
u8 pll_divout;
unsigned int pll_out;
u8 pll_cal_ratio;
};
static const struct cs43130_pll_params pll_ratio_table[] = {
{9600000, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151},
{9600000, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164},
{11289600, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128},
{11289600, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139},
{12000000, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120},
{12000000, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131},
{12288000, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118},
{12288000, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128},
{13000000, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111},
{13000000, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121},
{19200000, 0x03, 0x49, 0x800000, 0x00, 0x08, 22579200, 151},
{19200000, 0x03, 0x50, 0x000000, 0x00, 0x08, 24576000, 164},
{22579200, 0, 0, 0, 0, 0, 22579200, 0},
{22579200, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139},
{24000000, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120},
{24000000, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131},
{24576000, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118},
{24576000, 0, 0, 0, 0, 0, 24576000, 0},
{26000000, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111},
{26000000, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121},
};
static const struct cs43130_pll_params *cs43130_get_pll_table(
unsigned int freq_in, unsigned int freq_out)
{
int i;
for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
if (pll_ratio_table[i].pll_in == freq_in &&
pll_ratio_table[i].pll_out == freq_out)
return &pll_ratio_table[i];
}
return NULL;
}
static int cs43130_pll_config(struct snd_soc_component *component)
{
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
const struct cs43130_pll_params *pll_entry;
dev_dbg(component->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n",
cs43130->mclk, cs43130->mclk_int);
pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int);
if (!pll_entry)
return -EINVAL;
if (pll_entry->pll_cal_ratio == 0) {
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
CS43130_PLL_START_MASK, 0);
cs43130->pll_bypass = true;
return 0;
}
cs43130->pll_bypass = false;
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2,
CS43130_PLL_DIV_DATA_MASK,
pll_entry->pll_div_frac >>
CS43130_PLL_DIV_FRAC_0_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3,
CS43130_PLL_DIV_DATA_MASK,
pll_entry->pll_div_frac >>
CS43130_PLL_DIV_FRAC_1_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4,
CS43130_PLL_DIV_DATA_MASK,
pll_entry->pll_div_frac >>
CS43130_PLL_DIV_FRAC_2_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_PLL_SET_5,
pll_entry->pll_div_int);
regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout);
regmap_write(cs43130->regmap, CS43130_PLL_SET_7,
pll_entry->pll_cal_ratio);
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8,
CS43130_PLL_MODE_MASK,
pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT);
regmap_write(cs43130->regmap, CS43130_PLL_SET_9,
pll_entry->sclk_prediv);
regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
CS43130_PLL_START_MASK, 1);
return 0;
}
static int cs43130_set_pll(struct snd_soc_component *component, int pll_id, int source,
unsigned int freq_in, unsigned int freq_out)
{
int ret = 0;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
switch (freq_in) {
case 9600000:
case 11289600:
case 12000000:
case 12288000:
case 13000000:
case 19200000:
case 22579200:
case 24000000:
case 24576000:
case 26000000:
cs43130->mclk = freq_in;
break;
default:
dev_err(component->dev,
"unsupported pll input reference clock:%d\n", freq_in);
return -EINVAL;
}
switch (freq_out) {
case 22579200:
cs43130->mclk_int = freq_out;
break;
case 24576000:
cs43130->mclk_int = freq_out;
break;
default:
dev_err(component->dev,
"unsupported pll output ref clock: %u\n", freq_out);
return -EINVAL;
}
ret = cs43130_pll_config(component);
dev_dbg(component->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass);
return ret;
}
static int cs43130_change_clksrc(struct snd_soc_component *component,
enum cs43130_mclk_src_sel src)
{
int ret;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
int mclk_int_decoded;
if (src == cs43130->mclk_int_src) {
/* clk source has not changed */
return 0;
}
switch (cs43130->mclk_int) {
case CS43130_MCLK_22M:
mclk_int_decoded = CS43130_MCLK_22P5;
break;
case CS43130_MCLK_24M:
mclk_int_decoded = CS43130_MCLK_24P5;
break;
default:
dev_err(component->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int);
return -EINVAL;
}
switch (src) {
case CS43130_MCLK_SRC_EXT:
cs43130->pll_bypass = true;
cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT;
if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK,
1 << CS43130_PDN_XTAL_SHIFT);
} else {
reinit_completion(&cs43130->xtal_rdy);
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_RDY_INT_MASK, 0);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK, 0);
ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
msecs_to_jiffies(100));
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_RDY_INT_MASK,
1 << CS43130_XTAL_RDY_INT_SHIFT);
if (ret == 0) {
dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n");
return -ETIMEDOUT;
}
}
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_SRC_SEL_MASK,
src << CS43130_MCLK_SRC_SEL_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_INT_MASK,
mclk_int_decoded << CS43130_MCLK_INT_SHIFT);
usleep_range(150, 200);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_PLL_MASK,
1 << CS43130_PDN_PLL_SHIFT);
break;
case CS43130_MCLK_SRC_PLL:
cs43130->pll_bypass = false;
cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL;
if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK,
1 << CS43130_PDN_XTAL_SHIFT);
} else {
reinit_completion(&cs43130->xtal_rdy);
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_RDY_INT_MASK, 0);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK, 0);
ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
msecs_to_jiffies(100));
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_XTAL_RDY_INT_MASK,
1 << CS43130_XTAL_RDY_INT_SHIFT);
if (ret == 0) {
dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n");
return -ETIMEDOUT;
}
}
reinit_completion(&cs43130->pll_rdy);
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_PLL_RDY_INT_MASK, 0);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_PLL_MASK, 0);
ret = wait_for_completion_timeout(&cs43130->pll_rdy,
msecs_to_jiffies(100));
regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
CS43130_PLL_RDY_INT_MASK,
1 << CS43130_PLL_RDY_INT_SHIFT);
if (ret == 0) {
dev_err(component->dev, "Timeout waiting for PLL_READY interrupt\n");
return -ETIMEDOUT;
}
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_SRC_SEL_MASK,
src << CS43130_MCLK_SRC_SEL_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_INT_MASK,
mclk_int_decoded << CS43130_MCLK_INT_SHIFT);
usleep_range(150, 200);
break;
case CS43130_MCLK_SRC_RCO:
cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_SRC_SEL_MASK,
src << CS43130_MCLK_SRC_SEL_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
CS43130_MCLK_INT_MASK,
CS43130_MCLK_22P5 << CS43130_MCLK_INT_SHIFT);
usleep_range(150, 200);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_XTAL_MASK,
1 << CS43130_PDN_XTAL_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
CS43130_PDN_PLL_MASK,
1 << CS43130_PDN_PLL_SHIFT);
break;
default:
dev_err(component->dev, "Invalid MCLK source value\n");
return -EINVAL;
}
return 0;
}
static const struct cs43130_bitwidth_map cs43130_bitwidth_table[] = {
{8, CS43130_SP_BIT_SIZE_8, CS43130_CH_BIT_SIZE_8},
{16, CS43130_SP_BIT_SIZE_16, CS43130_CH_BIT_SIZE_16},
{24, CS43130_SP_BIT_SIZE_24, CS43130_CH_BIT_SIZE_24},
{32, CS43130_SP_BIT_SIZE_32, CS43130_CH_BIT_SIZE_32},
};
static const struct cs43130_bitwidth_map *cs43130_get_bitwidth_table(
unsigned int bitwidth)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs43130_bitwidth_table); i++) {
if (cs43130_bitwidth_table[i].bitwidth == bitwidth)
return &cs43130_bitwidth_table[i];
}
return NULL;
}
static int cs43130_set_bitwidth(int dai_id, unsigned int bitwidth_dai,
struct regmap *regmap)
{
const struct cs43130_bitwidth_map *bw_map;
bw_map = cs43130_get_bitwidth_table(bitwidth_dai);
if (!bw_map)
return -EINVAL;
switch (dai_id) {
case CS43130_ASP_PCM_DAI:
case CS43130_ASP_DOP_DAI:
regmap_update_bits(regmap, CS43130_ASP_CH_1_SZ_EN,
CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
regmap_update_bits(regmap, CS43130_ASP_CH_2_SZ_EN,
CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
regmap_update_bits(regmap, CS43130_SP_BITSIZE,
CS43130_ASP_BITSIZE_MASK, bw_map->sp_bit);
break;
case CS43130_XSP_DOP_DAI:
regmap_update_bits(regmap, CS43130_XSP_CH_1_SZ_EN,
CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
regmap_update_bits(regmap, CS43130_XSP_CH_2_SZ_EN,
CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
regmap_update_bits(regmap, CS43130_SP_BITSIZE,
CS43130_XSP_BITSIZE_MASK, bw_map->sp_bit <<
CS43130_XSP_BITSIZE_SHIFT);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct cs43130_rate_map cs43130_rate_table[] = {
{32000, CS43130_ASP_SPRATE_32K},
{44100, CS43130_ASP_SPRATE_44_1K},
{48000, CS43130_ASP_SPRATE_48K},
{88200, CS43130_ASP_SPRATE_88_2K},
{96000, CS43130_ASP_SPRATE_96K},
{176400, CS43130_ASP_SPRATE_176_4K},
{192000, CS43130_ASP_SPRATE_192K},
{352800, CS43130_ASP_SPRATE_352_8K},
{384000, CS43130_ASP_SPRATE_384K},
};
static const struct cs43130_rate_map *cs43130_get_rate_table(int fs)
{
int i;
for (i = 0; i < ARRAY_SIZE(cs43130_rate_table); i++) {
if (cs43130_rate_table[i].fs == fs)
return &cs43130_rate_table[i];
}
return NULL;
}
static const struct cs43130_clk_gen *cs43130_get_clk_gen(int mclk_int, int fs,
const struct cs43130_clk_gen *clk_gen_table, int len_clk_gen_table)
{
int i;
for (i = 0; i < len_clk_gen_table; i++) {
if (clk_gen_table[i].mclk_int == mclk_int &&
clk_gen_table[i].fs == fs)
return &clk_gen_table[i];
}
return NULL;
}
static int cs43130_set_sp_fmt(int dai_id, unsigned int bitwidth_sclk,
struct snd_pcm_hw_params *params,
struct cs43130_private *cs43130)
{
u16 frm_size;
u16 hi_size;
u8 frm_delay;
u8 frm_phase;
u8 frm_data;
u8 sclk_edge;
u8 lrck_edge;
u8 clk_data;
u8 loc_ch1;
u8 loc_ch2;
u8 dai_mode_val;
const struct cs43130_clk_gen *clk_gen;
switch (cs43130->dais[dai_id].dai_format) {
case SND_SOC_DAIFMT_I2S:
hi_size = bitwidth_sclk;
frm_delay = 2;
frm_phase = 0;
break;
case SND_SOC_DAIFMT_LEFT_J:
hi_size = bitwidth_sclk;
frm_delay = 2;
frm_phase = 1;
break;
case SND_SOC_DAIFMT_DSP_A:
hi_size = 1;
frm_delay = 2;
frm_phase = 1;
break;
case SND_SOC_DAIFMT_DSP_B:
hi_size = 1;
frm_delay = 0;
frm_phase = 1;
break;
default:
return -EINVAL;
}
switch (cs43130->dais[dai_id].dai_mode) {
case SND_SOC_DAIFMT_CBS_CFS:
dai_mode_val = 0;
break;
case SND_SOC_DAIFMT_CBM_CFM:
dai_mode_val = 1;
break;
default:
return -EINVAL;
}
frm_size = bitwidth_sclk * params_channels(params);
sclk_edge = 1;
lrck_edge = 0;
loc_ch1 = 0;
loc_ch2 = bitwidth_sclk * (params_channels(params) - 1);
frm_data = frm_delay & CS43130_SP_FSD_MASK;
frm_data |= (frm_phase << CS43130_SP_STP_SHIFT) & CS43130_SP_STP_MASK;
clk_data = lrck_edge & CS43130_SP_LCPOL_IN_MASK;
clk_data |= (lrck_edge << CS43130_SP_LCPOL_OUT_SHIFT) &
CS43130_SP_LCPOL_OUT_MASK;
clk_data |= (sclk_edge << CS43130_SP_SCPOL_IN_SHIFT) &
CS43130_SP_SCPOL_IN_MASK;
clk_data |= (sclk_edge << CS43130_SP_SCPOL_OUT_SHIFT) &
CS43130_SP_SCPOL_OUT_MASK;
clk_data |= (dai_mode_val << CS43130_SP_MODE_SHIFT) &
CS43130_SP_MODE_MASK;
switch (dai_id) {
case CS43130_ASP_PCM_DAI:
case CS43130_ASP_DOP_DAI:
regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,
CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
CS43130_SP_LCPR_LSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,
CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
CS43130_SP_LCPR_MSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,
CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
CS43130_SP_LCHI_LSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,
CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
CS43130_SP_LCHI_MSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data);
regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1);
regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2);
regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,
CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,
CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data);
break;
case CS43130_XSP_DOP_DAI:
regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1,
CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
CS43130_SP_LCPR_LSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2,
CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
CS43130_SP_LCPR_MSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1,
CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
CS43130_SP_LCHI_LSB_DATA_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2,
CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
CS43130_SP_LCHI_MSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data);
regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1);
regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2);
regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN,
CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN,
CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data);
break;
default:
return -EINVAL;
}
switch (frm_size) {
case 16:
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
params_rate(params),
cs43130_16_clk_gen,
ARRAY_SIZE(cs43130_16_clk_gen));
break;
case 32:
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
params_rate(params),
cs43130_32_clk_gen,
ARRAY_SIZE(cs43130_32_clk_gen));
break;
case 48:
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
params_rate(params),
cs43130_48_clk_gen,
ARRAY_SIZE(cs43130_48_clk_gen));
break;
case 64:
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
params_rate(params),
cs43130_64_clk_gen,
ARRAY_SIZE(cs43130_64_clk_gen));
break;
default:
return -EINVAL;
}
if (!clk_gen)
return -EINVAL;
switch (dai_id) {
case CS43130_ASP_PCM_DAI:
case CS43130_ASP_DOP_DAI:
regmap_write(cs43130->regmap, CS43130_ASP_DEN_1,
(clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >>
CS43130_SP_M_LSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_DEN_2,
(clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >>
CS43130_SP_M_MSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_NUM_1,
(clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >>
CS43130_SP_N_LSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_ASP_NUM_2,
(clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >>
CS43130_SP_N_MSB_DATA_SHIFT);
break;
case CS43130_XSP_DOP_DAI:
regmap_write(cs43130->regmap, CS43130_XSP_DEN_1,
(clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >>
CS43130_SP_M_LSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_DEN_2,
(clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >>
CS43130_SP_M_MSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_NUM_1,
(clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >>
CS43130_SP_N_LSB_DATA_SHIFT);
regmap_write(cs43130->regmap, CS43130_XSP_NUM_2,
(clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >>
CS43130_SP_N_MSB_DATA_SHIFT);
break;
default:
return -EINVAL;
}
return 0;
}
static int cs43130_pcm_dsd_mix(bool en, struct regmap *regmap)
{
if (en) {
regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
CS43130_MIX_PCM_PREP_MASK,
1 << CS43130_MIX_PCM_PREP_SHIFT);
usleep_range(6000, 6050);
regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
CS43130_MIX_PCM_DSD_MASK,
1 << CS43130_MIX_PCM_DSD_SHIFT);
} else {
regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
CS43130_MIX_PCM_DSD_MASK,
0 << CS43130_MIX_PCM_DSD_SHIFT);
usleep_range(1600, 1650);
regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
CS43130_MIX_PCM_PREP_MASK,
0 << CS43130_MIX_PCM_PREP_SHIFT);
}
return 0;
}
static int cs43130_dsd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
unsigned int required_clk;
u8 dsd_speed;
mutex_lock(&cs43130->clk_mutex);
if (!cs43130->clk_req) {
/* no DAI is currently using clk */
if (!(CS43130_MCLK_22M % params_rate(params)))
required_clk = CS43130_MCLK_22M;
else
required_clk = CS43130_MCLK_24M;
cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
if (cs43130->pll_bypass)
cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
else
cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
}
cs43130->clk_req++;
if (cs43130->clk_req == 2)
cs43130_pcm_dsd_mix(true, cs43130->regmap);
mutex_unlock(&cs43130->clk_mutex);
switch (params_rate(params)) {
case 176400:
dsd_speed = 0;
break;
case 352800:
dsd_speed = 1;
break;
default:
dev_err(component->dev, "Rate(%u) not supported\n",
params_rate(params));
return -EINVAL;
}
if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
CS43130_DSD_MASTER, CS43130_DSD_MASTER);
else
regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
CS43130_DSD_MASTER, 0);
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SPEED_MASK,
dsd_speed << CS43130_DSD_SPEED_SHIFT);
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_DSD <<
CS43130_DSD_SRC_SHIFT);
return 0;
}
static int cs43130_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
const struct cs43130_rate_map *rate_map;
unsigned int sclk = cs43130->dais[dai->id].sclk;
unsigned int bitwidth_sclk;
unsigned int bitwidth_dai = (unsigned int)(params_width(params));
unsigned int required_clk;
u8 dsd_speed;
mutex_lock(&cs43130->clk_mutex);
if (!cs43130->clk_req) {
/* no DAI is currently using clk */
if (!(CS43130_MCLK_22M % params_rate(params)))
required_clk = CS43130_MCLK_22M;
else
required_clk = CS43130_MCLK_24M;
cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
if (cs43130->pll_bypass)
cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
else
cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
}
cs43130->clk_req++;
if (cs43130->clk_req == 2)
cs43130_pcm_dsd_mix(true, cs43130->regmap);
mutex_unlock(&cs43130->clk_mutex);
switch (dai->id) {
case CS43130_ASP_DOP_DAI:
case CS43130_XSP_DOP_DAI:
/* DoP bitwidth is always 24-bit */
bitwidth_dai = 24;
sclk = params_rate(params) * bitwidth_dai *
params_channels(params);
switch (params_rate(params)) {
case 176400:
dsd_speed = 0;
break;
case 352800:
dsd_speed = 1;
break;
default:
dev_err(component->dev, "Rate(%u) not supported\n",
params_rate(params));
return -EINVAL;
}
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SPEED_MASK,
dsd_speed << CS43130_DSD_SPEED_SHIFT);
break;
case CS43130_ASP_PCM_DAI:
rate_map = cs43130_get_rate_table(params_rate(params));
if (!rate_map)
return -EINVAL;
regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val);
break;
default:
dev_err(component->dev, "Invalid DAI (%d)\n", dai->id);
return -EINVAL;
}
switch (dai->id) {
case CS43130_ASP_DOP_DAI:
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_ASP <<
CS43130_DSD_SRC_SHIFT);
break;
case CS43130_XSP_DOP_DAI:
regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_XSP <<
CS43130_DSD_SRC_SHIFT);
break;
}
if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
/* Calculate SCLK in master mode if unassigned */
sclk = params_rate(params) * bitwidth_dai *
params_channels(params);
if (!sclk) {
/* at this point, SCLK must be set */
dev_err(component->dev, "SCLK freq is not set\n");
return -EINVAL;
}
bitwidth_sclk = (sclk / params_rate(params)) / params_channels(params);
if (bitwidth_sclk < bitwidth_dai) {
dev_err(component->dev, "Format not supported: SCLK freq is too low\n");
return -EINVAL;
}
dev_dbg(component->dev,
"sclk = %u, fs = %d, bitwidth_dai = %u\n",
sclk, params_rate(params), bitwidth_dai);
dev_dbg(component->dev,
"bitwidth_sclk = %u, num_ch = %u\n",
bitwidth_sclk, params_channels(params));
cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap);
cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130);
return 0;
}
static int cs43130_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
mutex_lock(&cs43130->clk_mutex);
cs43130->clk_req--;
if (!cs43130->clk_req) {
/* no DAI is currently using clk */
cs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO);
cs43130_pcm_dsd_mix(false, cs43130->regmap);
}
mutex_unlock(&cs43130->clk_mutex);
return 0;
}
static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1);
static const char * const pcm_ch_text[] = {
"Left-Right Ch",
"Left-Left Ch",
"Right-Left Ch",
"Right-Right Ch",
};
static const struct reg_sequence pcm_ch_en_seq[] = {
{CS43130_DXD1, 0x99},
{0x180005, 0x8C},
{0x180007, 0xAB},
{0x180015, 0x31},
{0x180017, 0xB2},
{0x180025, 0x30},
{0x180027, 0x84},
{0x180035, 0x9C},
{0x180037, 0xAE},
{0x18000D, 0x24},
{0x18000F, 0xA3},
{0x18001D, 0x05},
{0x18001F, 0xD4},
{0x18002D, 0x0B},
{0x18002F, 0xC7},
{0x18003D, 0x71},
{0x18003F, 0xE7},
{CS43130_DXD1, 0},
};
static const struct reg_sequence pcm_ch_dis_seq[] = {
{CS43130_DXD1, 0x99},
{0x180005, 0x24},
{0x180007, 0xA3},
{0x180015, 0x05},
{0x180017, 0xD4},
{0x180025, 0x0B},
{0x180027, 0xC7},
{0x180035, 0x71},