/
tiomap3430.c
1806 lines (1661 loc) · 51.8 KB
/
tiomap3430.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* tiomap.c
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Processor Manager Driver for TI OMAP3430 EVM.
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <plat/dsp.h>
#include <linux/types.h>
/* ----------------------------------- Host OS */
#include <dspbridge/host_os.h>
#include <linux/mm.h>
#include <linux/mmzone.h>
/* ----------------------------------- DSP/BIOS Bridge */
#include <dspbridge/dbdefs.h>
/* ----------------------------------- OS Adaptation Layer */
#include <dspbridge/drv.h>
#include <dspbridge/sync.h>
/* ------------------------------------ Hardware Abstraction Layer */
#include <hw_defs.h>
#include <hw_mmu.h>
/* ----------------------------------- Link Driver */
#include <dspbridge/dspdefs.h>
#include <dspbridge/dspchnl.h>
#include <dspbridge/dspdeh.h>
#include <dspbridge/dspio.h>
#include <dspbridge/dspmsg.h>
#include <dspbridge/pwr.h>
#include <dspbridge/io_sm.h>
/* ----------------------------------- Platform Manager */
#include <dspbridge/dev.h>
#include <dspbridge/dspapi.h>
#include <dspbridge/dmm.h>
#include <dspbridge/wdt.h>
/* ----------------------------------- Local */
#include "_tiomap.h"
#include "_tiomap_pwr.h"
#include "tiomap_io.h"
/* Offset in shared mem to write to in order to synchronize start with DSP */
#define SHMSYNCOFFSET 4 /* GPP byte offset */
#define BUFFERSIZE 1024
#define TIHELEN_ACKTIMEOUT 10000
#define MMU_SECTION_ADDR_MASK 0xFFF00000
#define MMU_SSECTION_ADDR_MASK 0xFF000000
#define MMU_LARGE_PAGE_MASK 0xFFFF0000
#define MMU_SMALL_PAGE_MASK 0xFFFFF000
#define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
#define PAGES_II_LVL_TABLE 512
#define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT)
/*
* This is a totally ugly layer violation, but needed until
* omap_ctrl_set_dsp_boot*() are provided.
*/
#define OMAP3_IVA2_BOOTMOD_IDLE 1
#define OMAP2_CONTROL_GENERAL 0x270
#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
/* Forward Declarations: */
static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
u8 *host_buff,
u32 dsp_addr, u32 ul_num_bytes,
u32 mem_type);
static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
u32 dsp_addr);
static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
int *board_state);
static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt);
static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
u8 *host_buff,
u32 dsp_addr, u32 ul_num_bytes,
u32 mem_type);
static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
u32 brd_state);
static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
u32 dsp_dest_addr, u32 dsp_src_addr,
u32 ul_num_bytes, u32 mem_type);
static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
u8 *host_buff, u32 dsp_addr,
u32 ul_num_bytes, u32 mem_type);
static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
u32 ul_mpu_addr, u32 virt_addr,
u32 ul_num_bytes, u32 ul_map_attr,
struct page **mapped_pages);
static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
u32 virt_addr, u32 ul_num_bytes);
static int bridge_dev_create(struct bridge_dev_context
**dev_cntxt,
struct dev_object *hdev_obj,
struct cfg_hostres *config_param);
static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
u32 dw_cmd, void *pargs);
static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
static u32 user_va2_pa(struct mm_struct *mm, u32 address);
static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
u32 va, u32 size,
struct hw_mmu_map_attrs_t *map_attrs);
static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
u32 size, struct hw_mmu_map_attrs_t *attrs);
static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
u32 ul_mpu_addr, u32 virt_addr,
u32 ul_num_bytes,
struct hw_mmu_map_attrs_t *hw_attrs);
bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
/* ----------------------------------- Globals */
/* Attributes of L2 page tables for DSP MMU */
struct page_info {
u32 num_entries; /* Number of valid PTEs in the L2 PT */
};
/* Attributes used to manage the DSP MMU page tables */
struct pg_table_attrs {
spinlock_t pg_lock; /* Critical section object handle */
u32 l1_base_pa; /* Physical address of the L1 PT */
u32 l1_base_va; /* Virtual address of the L1 PT */
u32 l1_size; /* Size of the L1 PT */
u32 l1_tbl_alloc_pa;
/* Physical address of Allocated mem for L1 table. May not be aligned */
u32 l1_tbl_alloc_va;
/* Virtual address of Allocated mem for L1 table. May not be aligned */
u32 l1_tbl_alloc_sz;
/* Size of consistent memory allocated for L1 table.
* May not be aligned */
u32 l2_base_pa; /* Physical address of the L2 PT */
u32 l2_base_va; /* Virtual address of the L2 PT */
u32 l2_size; /* Size of the L2 PT */
u32 l2_tbl_alloc_pa;
/* Physical address of Allocated mem for L2 table. May not be aligned */
u32 l2_tbl_alloc_va;
/* Virtual address of Allocated mem for L2 table. May not be aligned */
u32 l2_tbl_alloc_sz;
/* Size of consistent memory allocated for L2 table.
* May not be aligned */
u32 l2_num_pages; /* Number of allocated L2 PT */
/* Array [l2_num_pages] of L2 PT info structs */
struct page_info *pg_info;
};
/*
* This Bridge driver's function interface table.
*/
static struct bridge_drv_interface drv_interface_fxns = {
/* Bridge API ver. for which this bridge driver is built. */
BRD_API_MAJOR_VERSION,
BRD_API_MINOR_VERSION,
bridge_dev_create,
bridge_dev_destroy,
bridge_dev_ctrl,
bridge_brd_monitor,
bridge_brd_start,
bridge_brd_stop,
bridge_brd_status,
bridge_brd_read,
bridge_brd_write,
bridge_brd_set_state,
bridge_brd_mem_copy,
bridge_brd_mem_write,
bridge_brd_mem_map,
bridge_brd_mem_un_map,
/* The following CHNL functions are provided by chnl_io.lib: */
bridge_chnl_create,
bridge_chnl_destroy,
bridge_chnl_open,
bridge_chnl_close,
bridge_chnl_add_io_req,
bridge_chnl_get_ioc,
bridge_chnl_cancel_io,
bridge_chnl_flush_io,
bridge_chnl_get_info,
bridge_chnl_get_mgr_info,
bridge_chnl_idle,
bridge_chnl_register_notify,
/* The following IO functions are provided by chnl_io.lib: */
bridge_io_create,
bridge_io_destroy,
bridge_io_on_loaded,
bridge_io_get_proc_load,
/* The following msg_ctrl functions are provided by chnl_io.lib: */
bridge_msg_create,
bridge_msg_create_queue,
bridge_msg_delete,
bridge_msg_delete_queue,
bridge_msg_get,
bridge_msg_put,
bridge_msg_register_notify,
bridge_msg_set_queue_id,
};
static struct notifier_block dsp_mbox_notifier = {
.notifier_call = io_mbox_msg,
};
static inline void flush_all(struct bridge_dev_context *dev_context)
{
if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
dev_context->brd_state == BRD_HIBERNATION)
wake_dsp(dev_context, NULL);
hw_mmu_tlb_flush_all(dev_context->dsp_mmu_base);
}
static void bad_page_dump(u32 pa, struct page *pg)
{
pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
pr_emerg("Bad page state in process '%s'\n"
"page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
"Backtrace:\n",
current->comm, pg, (int)(2 * sizeof(unsigned long)),
(unsigned long)pg->flags, pg->mapping,
page_mapcount(pg), page_count(pg));
dump_stack();
}
/*
* ======== bridge_drv_entry ========
* purpose:
* Bridge Driver entry point.
*/
void bridge_drv_entry(struct bridge_drv_interface **drv_intf,
const char *driver_file_name)
{
if (strcmp(driver_file_name, "UMA") == 0)
*drv_intf = &drv_interface_fxns;
else
dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
}
/*
* ======== bridge_brd_monitor ========
* purpose:
* This bridge_brd_monitor puts DSP into a Loadable state.
* i.e Application can load and start the device.
*
* Preconditions:
* Device in 'OFF' state.
*/
static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
{
struct bridge_dev_context *dev_context = dev_ctxt;
u32 temp;
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
OMAP_POWERSTATEST_MASK;
if (!(temp & 0x02)) {
/* IVA2 is not in ON state */
/* Read and set PM_PWSTCTRL_IVA2 to ON */
(*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
/* Set the SW supervised state transition */
(*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
/* Wait until the state has moved to ON */
while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
OMAP_INTRANSITION_MASK)
;
/* Disable Automatic transition */
(*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
}
(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
dsp_clk_enable(DSP_CLK_IVA2);
/* set the device state to IDLE */
dev_context->brd_state = BRD_IDLE;
return 0;
}
/*
* ======== bridge_brd_read ========
* purpose:
* Reads buffers for DSP memory.
*/
static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
u8 *host_buff, u32 dsp_addr,
u32 ul_num_bytes, u32 mem_type)
{
int status = 0;
struct bridge_dev_context *dev_context = dev_ctxt;
u32 offset;
u32 dsp_base_addr = dev_ctxt->dsp_base_addr;
if (dsp_addr < dev_context->dsp_start_add) {
status = -EPERM;
return status;
}
/* change here to account for the 3 bands of the DSP internal memory */
if ((dsp_addr - dev_context->dsp_start_add) <
dev_context->internal_size) {
offset = dsp_addr - dev_context->dsp_start_add;
} else {
status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
ul_num_bytes, mem_type);
return status;
}
/* copy the data from DSP memory, */
memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes);
return status;
}
/*
* ======== bridge_brd_set_state ========
* purpose:
* This routine updates the Board status.
*/
static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
u32 brd_state)
{
int status = 0;
struct bridge_dev_context *dev_context = dev_ctxt;
dev_context->brd_state = brd_state;
return status;
}
/*
* ======== bridge_brd_start ========
* purpose:
* Initializes DSP MMU and Starts DSP.
*
* Preconditions:
* a) DSP domain is 'ACTIVE'.
* b) DSP_RST1 is asserted.
* b) DSP_RST2 is released.
*/
static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
u32 dsp_addr)
{
int status = 0;
struct bridge_dev_context *dev_context = dev_ctxt;
u32 dw_sync_addr = 0;
u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
/* Offset of shm_base_virt from tlb_base_virt */
u32 ul_shm_offset_virt;
s32 entry_ndx;
s32 itmp_entry_ndx = 0; /* DSP-MMU TLB entry base address */
struct cfg_hostres *resources = NULL;
u32 temp;
u32 ul_dsp_clk_rate;
u32 ul_dsp_clk_addr;
u32 ul_bios_gp_timer;
u32 clk_cmd;
struct io_mgr *hio_mgr;
u32 ul_load_monitor_timer;
u32 wdt_en = 0;
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
/* The device context contains all the mmu setup info from when the
* last dsp base image was loaded. The first entry is always
* SHMMEM base. */
/* Get SHM_BEG - convert to byte address */
(void)dev_get_symbol(dev_context->dev_obj, SHMBASENAME,
&ul_shm_base_virt);
ul_shm_base_virt *= DSPWORDSIZE;
/* DSP Virtual address */
ul_tlb_base_virt = dev_context->atlb_entry[0].dsp_va;
ul_shm_offset_virt =
ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
/* Kernel logical address */
ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
/* 2nd wd is used as sync field */
dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
/* Write a signature into the shm base + offset; this will
* get cleared when the DSP program starts. */
if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
pr_err("%s: Illegal SM base\n", __func__);
status = -EPERM;
} else
__raw_writel(0xffffffff, dw_sync_addr);
if (!status) {
resources = dev_context->resources;
if (!resources)
status = -EPERM;
/* Assert RST1 i.e only the RST only for DSP megacell */
if (!status) {
/*
* XXX: ioremapping MUST be removed once ctrl
* function is made available.
*/
void __iomem *ctrl = ioremap(OMAP343X_CTRL_BASE, SZ_4K);
if (!ctrl)
return -ENOMEM;
(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
OMAP2_RM_RSTCTRL);
/* Mask address with 1K for compatibility */
__raw_writel(dsp_addr & OMAP3_IVA2_BOOTADDR_MASK,
ctrl + OMAP343X_CONTROL_IVA2_BOOTADDR);
/*
* Set bootmode to self loop if dsp_debug flag is true
*/
__raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
ctrl + OMAP343X_CONTROL_IVA2_BOOTMOD);
iounmap(ctrl);
}
}
if (!status) {
/* Reset and Unreset the RST2, so that BOOTADDR is copied to
* IVA2 SYSC register */
(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
udelay(100);
(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
udelay(100);
/* Disbale the DSP MMU */
hw_mmu_disable(resources->dmmu_base);
/* Disable TWL */
hw_mmu_twl_disable(resources->dmmu_base);
/* Only make TLB entry if both addresses are non-zero */
for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB;
entry_ndx++) {
struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx];
struct hw_mmu_map_attrs_t map_attrs = {
.endianism = e->endianism,
.element_size = e->elem_size,
.mixed_size = e->mixed_mode,
};
if (!e->gpp_pa || !e->dsp_va)
continue;
dev_dbg(bridge,
"MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x",
itmp_entry_ndx,
e->gpp_pa,
e->dsp_va,
e->size);
hw_mmu_tlb_add(dev_context->dsp_mmu_base,
e->gpp_pa,
e->dsp_va,
e->size,
itmp_entry_ndx,
&map_attrs, 1, 1);
itmp_entry_ndx++;
}
}
/* Lock the above TLB entries and get the BIOS and load monitor timer
* information */
if (!status) {
hw_mmu_num_locked_set(resources->dmmu_base, itmp_entry_ndx);
hw_mmu_victim_num_set(resources->dmmu_base, itmp_entry_ndx);
hw_mmu_ttb_set(resources->dmmu_base,
dev_context->pt_attrs->l1_base_pa);
hw_mmu_twl_enable(resources->dmmu_base);
/* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
temp = __raw_readl((resources->dmmu_base) + 0x10);
temp = (temp & 0xFFFFFFEF) | 0x11;
__raw_writel(temp, (resources->dmmu_base) + 0x10);
/* Let the DSP MMU run */
hw_mmu_enable(resources->dmmu_base);
/* Enable the BIOS clock */
(void)dev_get_symbol(dev_context->dev_obj,
BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
(void)dev_get_symbol(dev_context->dev_obj,
BRIDGEINIT_LOADMON_GPTIMER,
&ul_load_monitor_timer);
}
if (!status) {
if (ul_load_monitor_timer != 0xFFFF) {
clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
ul_load_monitor_timer;
dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
} else {
dev_dbg(bridge, "Not able to get the symbol for Load "
"Monitor Timer\n");
}
}
if (!status) {
if (ul_bios_gp_timer != 0xFFFF) {
clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
ul_bios_gp_timer;
dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
} else {
dev_dbg(bridge,
"Not able to get the symbol for BIOS Timer\n");
}
}
if (!status) {
/* Set the DSP clock rate */
(void)dev_get_symbol(dev_context->dev_obj,
"_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
/*Set Autoidle Mode for IVA2 PLL */
(*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
if ((unsigned int *)ul_dsp_clk_addr != NULL) {
/* Get the clock rate */
ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
__func__, ul_dsp_clk_rate);
(void)bridge_brd_write(dev_context,
(u8 *) &ul_dsp_clk_rate,
ul_dsp_clk_addr, sizeof(u32), 0);
}
/*
* Enable Mailbox events and also drain any pending
* stale messages.
*/
dev_context->mbox = omap_mbox_get("dsp", &dsp_mbox_notifier);
if (IS_ERR(dev_context->mbox)) {
dev_context->mbox = NULL;
pr_err("%s: Failed to get dsp mailbox handle\n",
__func__);
status = -EPERM;
}
}
if (!status) {
/*PM_IVA2GRPSEL_PER = 0xC0;*/
temp = readl(resources->per_pm_base + 0xA8);
temp = (temp & 0xFFFFFF30) | 0xC0;
writel(temp, resources->per_pm_base + 0xA8);
/*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
temp = readl(resources->per_pm_base + 0xA4);
temp = (temp & 0xFFFFFF3F);
writel(temp, resources->per_pm_base + 0xA4);
/*CM_SLEEPDEP_PER |= 0x04; */
temp = readl(resources->per_base + 0x44);
temp = (temp & 0xFFFFFFFB) | 0x04;
writel(temp, resources->per_base + 0x44);
/*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
(*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
/* Let DSP go */
dev_dbg(bridge, "%s Unreset\n", __func__);
/* Enable DSP MMU Interrupts */
hw_mmu_event_enable(resources->dmmu_base,
HW_MMU_ALL_INTERRUPTS);
/* release the RST1, DSP starts executing now .. */
(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr);
dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr);
if (dsp_debug)
while (__raw_readw(dw_sync_addr))
;
/* Wait for DSP to clear word in shared memory */
/* Read the Location */
if (!wait_for_start(dev_context, dw_sync_addr))
status = -ETIMEDOUT;
dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en);
if (wdt_en) {
/* Start wdt */
dsp_wdt_sm_set((void *)ul_shm_base);
dsp_wdt_enable(true);
}
status = dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
if (hio_mgr) {
io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
/* Write the synchronization bit to indicate the
* completion of OPP table update to DSP
*/
__raw_writel(0XCAFECAFE, dw_sync_addr);
/* update board state */
dev_context->brd_state = BRD_RUNNING;
/* (void)chnlsm_enable_interrupt(dev_context); */
} else {
dev_context->brd_state = BRD_UNKNOWN;
}
}
return status;
}
/*
* ======== bridge_brd_stop ========
* purpose:
* Puts DSP in self loop.
*
* Preconditions :
* a) None
*/
static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
{
int status = 0;
struct bridge_dev_context *dev_context = dev_ctxt;
struct pg_table_attrs *pt_attrs;
u32 dsp_pwr_state;
struct omap_dsp_platform_data *pdata =
omap_dspbridge_dev->dev.platform_data;
if (dev_context->brd_state == BRD_STOPPED)
return status;
/* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
* before turning off the clocks.. This is to ensure that there are no
* pending L3 or other transactons from IVA2 */
dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
OMAP_POWERSTATEST_MASK;
if (dsp_pwr_state != PWRDM_POWER_OFF) {
(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
mdelay(10);
/* IVA2 is not in OFF state */
/* Set PM_PWSTCTRL_IVA2 to OFF */
(*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
/* Set the SW supervised state transition for Sleep */
(*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
}
udelay(10);
/* Release the Ext Base virtual Address as the next DSP Program
* may have a different load address */
if (dev_context->dsp_ext_base_addr)
dev_context->dsp_ext_base_addr = 0;
dev_context->brd_state = BRD_STOPPED; /* update board state */
dsp_wdt_enable(false);
/* This is a good place to clear the MMU page tables as well */
if (dev_context->pt_attrs) {
pt_attrs = dev_context->pt_attrs;
memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
memset((u8 *) pt_attrs->pg_info, 0x00,
(pt_attrs->l2_num_pages * sizeof(struct page_info)));
}
/* Disable the mailbox interrupts */
if (dev_context->mbox) {
omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
omap_mbox_put(dev_context->mbox, &dsp_mbox_notifier);
dev_context->mbox = NULL;
}
/* Reset IVA2 clocks*/
(*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK |
OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
dsp_clock_disable_all(dev_context->dsp_per_clks);
dsp_clk_disable(DSP_CLK_IVA2);
return status;
}
/*
* ======== bridge_brd_status ========
* Returns the board status.
*/
static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
int *board_state)
{
struct bridge_dev_context *dev_context = dev_ctxt;
*board_state = dev_context->brd_state;
return 0;
}
/*
* ======== bridge_brd_write ========
* Copies the buffers to DSP internal or external memory.
*/
static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
u8 *host_buff, u32 dsp_addr,
u32 ul_num_bytes, u32 mem_type)
{
int status = 0;
struct bridge_dev_context *dev_context = dev_ctxt;
if (dsp_addr < dev_context->dsp_start_add) {
status = -EPERM;
return status;
}
if ((dsp_addr - dev_context->dsp_start_add) <
dev_context->internal_size) {
status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
ul_num_bytes, mem_type);
} else {
status = write_ext_dsp_data(dev_context, host_buff, dsp_addr,
ul_num_bytes, mem_type, false);
}
return status;
}
/*
* ======== bridge_dev_create ========
* Creates a driver object. Puts DSP in self loop.
*/
static int bridge_dev_create(struct bridge_dev_context
**dev_cntxt,
struct dev_object *hdev_obj,
struct cfg_hostres *config_param)
{
int status = 0;
struct bridge_dev_context *dev_context = NULL;
s32 entry_ndx;
struct cfg_hostres *resources = config_param;
struct pg_table_attrs *pt_attrs;
u32 pg_tbl_pa;
u32 pg_tbl_va;
u32 align_size;
struct drv_data *drv_datap = dev_get_drvdata(bridge);
/* Allocate and initialize a data structure to contain the bridge driver
* state, which becomes the context for later calls into this driver */
dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
if (!dev_context) {
status = -ENOMEM;
goto func_end;
}
dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;
dev_context->self_loop = (u32) NULL;
dev_context->dsp_per_clks = 0;
dev_context->internal_size = OMAP_DSP_SIZE;
/* Clear dev context MMU table entries.
* These get set on bridge_io_on_loaded() call after program loaded. */
for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
dev_context->atlb_entry[entry_ndx].gpp_pa =
dev_context->atlb_entry[entry_ndx].dsp_va = 0;
}
dev_context->dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
(config_param->
mem_base
[3]),
config_param->
mem_length
[3]);
if (!dev_context->dsp_base_addr)
status = -EPERM;
pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
if (pt_attrs != NULL) {
pt_attrs->l1_size = SZ_16K; /* 4096 entries of 32 bits */
align_size = pt_attrs->l1_size;
/* Align sizes are expected to be power of 2 */
/* we like to get aligned on L1 table size */
pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
align_size, &pg_tbl_pa);
/* Check if the PA is aligned for us */
if ((pg_tbl_pa) & (align_size - 1)) {
/* PA not aligned to page table size ,
* try with more allocation and align */
mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
pt_attrs->l1_size);
/* we like to get aligned on L1 table size */
pg_tbl_va =
(u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
align_size, &pg_tbl_pa);
/* We should be able to get aligned table now */
pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
/* Align the PA to the next 'align' boundary */
pt_attrs->l1_base_pa =
((pg_tbl_pa) +
(align_size - 1)) & (~(align_size - 1));
pt_attrs->l1_base_va =
pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
} else {
/* We got aligned PA, cool */
pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
pt_attrs->l1_base_pa = pg_tbl_pa;
pt_attrs->l1_base_va = pg_tbl_va;
}
if (pt_attrs->l1_base_va)
memset((u8 *) pt_attrs->l1_base_va, 0x00,
pt_attrs->l1_size);
/* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
* L4 pages */
pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
pt_attrs->l2_num_pages;
align_size = 4; /* Make it u32 aligned */
/* we like to get aligned on L1 table size */
pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
align_size, &pg_tbl_pa);
pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
pt_attrs->l2_base_pa = pg_tbl_pa;
pt_attrs->l2_base_va = pg_tbl_va;
if (pt_attrs->l2_base_va)
memset((u8 *) pt_attrs->l2_base_va, 0x00,
pt_attrs->l2_size);
pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
sizeof(struct page_info), GFP_KERNEL);
dev_dbg(bridge,
"L1 pa %x, va %x, size %x\n L2 pa %x, va "
"%x, size %x\n", pt_attrs->l1_base_pa,
pt_attrs->l1_base_va, pt_attrs->l1_size,
pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
pt_attrs->l2_size);
dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
}
if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
(pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
dev_context->pt_attrs = pt_attrs;
else
status = -ENOMEM;
if (!status) {
spin_lock_init(&pt_attrs->pg_lock);
dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
/* Set the Clock Divisor for the DSP module */
udelay(5);
/* MMU address is obtained from the host
* resources struct */
dev_context->dsp_mmu_base = resources->dmmu_base;
}
if (!status) {
dev_context->dev_obj = hdev_obj;
/* Store current board state. */
dev_context->brd_state = BRD_UNKNOWN;
dev_context->resources = resources;
dsp_clk_enable(DSP_CLK_IVA2);
bridge_brd_stop(dev_context);
/* Return ptr to our device state to the DSP API for storage */
*dev_cntxt = dev_context;
} else {
if (pt_attrs != NULL) {
kfree(pt_attrs->pg_info);
if (pt_attrs->l2_tbl_alloc_va) {
mem_free_phys_mem((void *)
pt_attrs->l2_tbl_alloc_va,
pt_attrs->l2_tbl_alloc_pa,
pt_attrs->l2_tbl_alloc_sz);
}
if (pt_attrs->l1_tbl_alloc_va) {
mem_free_phys_mem((void *)
pt_attrs->l1_tbl_alloc_va,
pt_attrs->l1_tbl_alloc_pa,
pt_attrs->l1_tbl_alloc_sz);
}
}
kfree(pt_attrs);
kfree(dev_context);
}
func_end:
return status;
}
/*
* ======== bridge_dev_ctrl ========
* Receives device specific commands.
*/
static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
u32 dw_cmd, void *pargs)
{
int status = 0;
struct bridge_ioctl_extproc *pa_ext_proc =
(struct bridge_ioctl_extproc *)pargs;
s32 ndx;
switch (dw_cmd) {
case BRDIOCTL_CHNLREAD:
break;
case BRDIOCTL_CHNLWRITE:
break;
case BRDIOCTL_SETMMUCONFIG:
/* store away dsp-mmu setup values for later use */
for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
dev_context->atlb_entry[ndx] = *pa_ext_proc;
break;
case BRDIOCTL_DEEPSLEEP:
case BRDIOCTL_EMERGENCYSLEEP:
/* Currently only DSP Idle is supported Need to update for
* later releases */
status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
break;
case BRDIOCTL_WAKEUP:
status = wake_dsp(dev_context, pargs);
break;
case BRDIOCTL_CLK_CTRL:
status = 0;
/* Looking For Baseport Fix for Clocks */
status = dsp_peripheral_clk_ctrl(dev_context, pargs);
break;
case BRDIOCTL_PWR_HIBERNATE:
status = handle_hibernation_from_dsp(dev_context);
break;
case BRDIOCTL_PRESCALE_NOTIFY:
status = pre_scale_dsp(dev_context, pargs);
break;
case BRDIOCTL_POSTSCALE_NOTIFY:
status = post_scale_dsp(dev_context, pargs);
break;
case BRDIOCTL_CONSTRAINT_REQUEST:
status = handle_constraints_set(dev_context, pargs);
break;
default:
status = -EPERM;
break;
}
return status;
}
/*
* ======== bridge_dev_destroy ========
* Destroys the driver object.
*/
static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
{
struct pg_table_attrs *pt_attrs;
int status = 0;
struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
dev_ctxt;
struct cfg_hostres *host_res;
u32 shm_size;
struct drv_data *drv_datap = dev_get_drvdata(bridge);
/* It should never happen */
if (!dev_ctxt)
return -EFAULT;
/* first put the device to stop state */
bridge_brd_stop(dev_context);
if (dev_context->pt_attrs) {
pt_attrs = dev_context->pt_attrs;
kfree(pt_attrs->pg_info);
if (pt_attrs->l2_tbl_alloc_va) {
mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
pt_attrs->l2_tbl_alloc_pa,
pt_attrs->l2_tbl_alloc_sz);
}
if (pt_attrs->l1_tbl_alloc_va) {
mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
pt_attrs->l1_tbl_alloc_pa,
pt_attrs->l1_tbl_alloc_sz);
}
kfree(pt_attrs);
}
if (dev_context->resources) {
host_res = dev_context->resources;