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i2c-npcm7xx.c
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i2c-npcm7xx.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Nuvoton NPCM7xx I2C Controller driver
*
* Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/irq.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
enum i2c_mode {
I2C_MASTER,
I2C_SLAVE,
};
/*
* External I2C Interface driver xfer indication values, which indicate status
* of the bus.
*/
enum i2c_state_ind {
I2C_NO_STATUS_IND = 0,
I2C_SLAVE_RCV_IND,
I2C_SLAVE_XMIT_IND,
I2C_SLAVE_XMIT_MISSING_DATA_IND,
I2C_SLAVE_RESTART_IND,
I2C_SLAVE_DONE_IND,
I2C_MASTER_DONE_IND,
I2C_NACK_IND,
I2C_BUS_ERR_IND,
I2C_WAKE_UP_IND,
I2C_BLOCK_BYTES_ERR_IND,
I2C_SLAVE_RCV_MISSING_DATA_IND,
};
/*
* Operation type values (used to define the operation currently running)
* module is interrupt driven, on each interrupt the current operation is
* checked to see if the module is currently reading or writing.
*/
enum i2c_oper {
I2C_NO_OPER = 0,
I2C_WRITE_OPER,
I2C_READ_OPER,
};
/* I2C Bank (module had 2 banks of registers) */
enum i2c_bank {
I2C_BANK_0 = 0,
I2C_BANK_1,
};
/* Internal I2C states values (for the I2C module state machine). */
enum i2c_state {
I2C_DISABLE = 0,
I2C_IDLE,
I2C_MASTER_START,
I2C_SLAVE_MATCH,
I2C_OPER_STARTED,
I2C_STOP_PENDING,
};
#if IS_ENABLED(CONFIG_I2C_SLAVE)
/* Module supports setting multiple own slave addresses */
enum i2c_addr {
I2C_SLAVE_ADDR1 = 0,
I2C_SLAVE_ADDR2,
I2C_SLAVE_ADDR3,
I2C_SLAVE_ADDR4,
I2C_SLAVE_ADDR5,
I2C_SLAVE_ADDR6,
I2C_SLAVE_ADDR7,
I2C_SLAVE_ADDR8,
I2C_SLAVE_ADDR9,
I2C_SLAVE_ADDR10,
I2C_GC_ADDR,
I2C_ARP_ADDR,
};
#endif
/* init register and default value required to enable module */
#define NPCM_I2CSEGCTL 0xE4
/* Common regs */
#define NPCM_I2CSDA 0x00
#define NPCM_I2CST 0x02
#define NPCM_I2CCST 0x04
#define NPCM_I2CCTL1 0x06
#define NPCM_I2CADDR1 0x08
#define NPCM_I2CCTL2 0x0A
#define NPCM_I2CADDR2 0x0C
#define NPCM_I2CCTL3 0x0E
#define NPCM_I2CCST2 0x18
#define NPCM_I2CCST3 0x19
#define I2C_VER 0x1F
/* BANK 0 regs */
#define NPCM_I2CADDR3 0x10
#define NPCM_I2CADDR7 0x11
#define NPCM_I2CADDR4 0x12
#define NPCM_I2CADDR8 0x13
#define NPCM_I2CADDR5 0x14
#define NPCM_I2CADDR9 0x15
#define NPCM_I2CADDR6 0x16
#define NPCM_I2CADDR10 0x17
#define NPCM_I2CCTL4 0x1A
#define NPCM_I2CCTL5 0x1B
#define NPCM_I2CSCLLT 0x1C /* SCL Low Time */
#define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */
#define NPCM_I2CSCLHT 0x1E /* SCL High Time */
/* BANK 1 regs */
#define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */
#define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
#define NPCM_I2CT_OUT 0x14 /* Bus T.O. */
#define NPCM_I2CPEC 0x16 /* PEC Data */
#define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
#define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
#define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
#if IS_ENABLED(CONFIG_I2C_SLAVE)
/*
* npcm_i2caddr array:
* The module supports having multiple own slave addresses.
* Since the addr regs are sprinkled all over the address space,
* use this array to get the address or each register.
*/
#define I2C_NUM_OWN_ADDR 2
#define I2C_NUM_OWN_ADDR_SUPPORTED 2
static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
NPCM_I2CADDR1, NPCM_I2CADDR2,
};
#endif
/* NPCM_I2CST reg fields */
#define NPCM_I2CST_XMIT BIT(0) /* Transmit mode */
#define NPCM_I2CST_MASTER BIT(1) /* Master mode */
#define NPCM_I2CST_NMATCH BIT(2) /* New match */
#define NPCM_I2CST_STASTR BIT(3) /* Stall after start */
#define NPCM_I2CST_NEGACK BIT(4) /* Negative ACK */
#define NPCM_I2CST_BER BIT(5) /* Bus error */
#define NPCM_I2CST_SDAST BIT(6) /* SDA status */
#define NPCM_I2CST_SLVSTP BIT(7) /* Slave stop */
/* NPCM_I2CCST reg fields */
#define NPCM_I2CCST_BUSY BIT(0) /* Busy */
#define NPCM_I2CCST_BB BIT(1) /* Bus busy */
#define NPCM_I2CCST_MATCH BIT(2) /* Address match */
#define NPCM_I2CCST_GCMATCH BIT(3) /* Global call match */
#define NPCM_I2CCST_TSDA BIT(4) /* Test SDA line */
#define NPCM_I2CCST_TGSCL BIT(5) /* Toggle SCL line */
#define NPCM_I2CCST_MATCHAF BIT(6) /* Match address field */
#define NPCM_I2CCST_ARPMATCH BIT(7) /* ARP address match */
/* NPCM_I2CCTL1 reg fields */
#define NPCM_I2CCTL1_START BIT(0) /* Generate start condition */
#define NPCM_I2CCTL1_STOP BIT(1) /* Generate stop condition */
#define NPCM_I2CCTL1_INTEN BIT(2) /* Interrupt enable */
#define NPCM_I2CCTL1_EOBINTE BIT(3)
#define NPCM_I2CCTL1_ACK BIT(4)
#define NPCM_I2CCTL1_GCMEN BIT(5) /* Global call match enable */
#define NPCM_I2CCTL1_NMINTE BIT(6) /* New match interrupt enable */
#define NPCM_I2CCTL1_STASTRE BIT(7) /* Stall after start enable */
/* RW1S fields (inside a RW reg): */
#define NPCM_I2CCTL1_RWS \
(NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
/* npcm_i2caddr reg fields */
#define NPCM_I2CADDR_A GENMASK(6, 0) /* Address */
#define NPCM_I2CADDR_SAEN BIT(7) /* Slave address enable */
/* NPCM_I2CCTL2 reg fields */
#define I2CCTL2_ENABLE BIT(0) /* Module enable */
#define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) /* Bits 0:6 of frequency divisor */
/* NPCM_I2CCTL3 reg fields */
#define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) /* Bits 7:8 of frequency divisor */
#define I2CCTL3_ARPMEN BIT(2) /* ARP match enable */
#define I2CCTL3_IDL_START BIT(3)
#define I2CCTL3_400K_MODE BIT(4)
#define I2CCTL3_BNK_SEL BIT(5)
#define I2CCTL3_SDA_LVL BIT(6)
#define I2CCTL3_SCL_LVL BIT(7)
/* NPCM_I2CCST2 reg fields */
#define NPCM_I2CCST2_MATCHA1F BIT(0)
#define NPCM_I2CCST2_MATCHA2F BIT(1)
#define NPCM_I2CCST2_MATCHA3F BIT(2)
#define NPCM_I2CCST2_MATCHA4F BIT(3)
#define NPCM_I2CCST2_MATCHA5F BIT(4)
#define NPCM_I2CCST2_MATCHA6F BIT(5)
#define NPCM_I2CCST2_MATCHA7F BIT(5)
#define NPCM_I2CCST2_INTSTS BIT(7)
/* NPCM_I2CCST3 reg fields */
#define NPCM_I2CCST3_MATCHA8F BIT(0)
#define NPCM_I2CCST3_MATCHA9F BIT(1)
#define NPCM_I2CCST3_MATCHA10F BIT(2)
#define NPCM_I2CCST3_EO_BUSY BIT(7)
/* NPCM_I2CCTL4 reg fields */
#define I2CCTL4_HLDT GENMASK(5, 0)
#define I2CCTL4_LVL_WE BIT(7)
/* NPCM_I2CCTL5 reg fields */
#define I2CCTL5_DBNCT GENMASK(3, 0)
/* NPCM_I2CFIF_CTS reg fields */
#define NPCM_I2CFIF_CTS_RXF_TXE BIT(1)
#define NPCM_I2CFIF_CTS_RFTE_IE BIT(3)
#define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6)
#define NPCM_I2CFIF_CTS_SLVRSTR BIT(7)
/* NPCM_I2CTXF_CTL reg field */
#define NPCM_I2CTXF_CTL_THR_TXIE BIT(6)
/* NPCM_I2CT_OUT reg fields */
#define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0)
#define NPCM_I2CT_OUT_T_OUTIE BIT(6)
#define NPCM_I2CT_OUT_T_OUTST BIT(7)
/* NPCM_I2CTXF_STS reg fields */
#define NPCM_I2CTXF_STS_TX_THST BIT(6)
/* NPCM_I2CRXF_STS reg fields */
#define NPCM_I2CRXF_STS_RX_THST BIT(6)
/* NPCM_I2CFIF_CTL reg fields */
#define NPCM_I2CFIF_CTL_FIFO_EN BIT(4)
/* NPCM_I2CRXF_CTL reg fields */
#define NPCM_I2CRXF_CTL_THR_RXIE BIT(6)
#define MAX_I2C_HW_FIFO_SIZE 32
/* I2C_VER reg fields */
#define I2C_VER_VERSION GENMASK(6, 0)
#define I2C_VER_FIFO_EN BIT(7)
/* stall/stuck timeout in us */
#define DEFAULT_STALL_COUNT 25
/* SCLFRQ field position */
#define SCLFRQ_0_TO_6 GENMASK(6, 0)
#define SCLFRQ_7_TO_8 GENMASK(8, 7)
/* supported clk settings. values in Hz. */
#define I2C_FREQ_MIN_HZ 10000
#define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ
struct npcm_i2c_data {
u8 fifo_size;
u32 segctl_init_val;
u8 txf_sts_tx_bytes;
u8 rxf_sts_rx_bytes;
u8 rxf_ctl_last_pec;
};
static const struct npcm_i2c_data npxm7xx_i2c_data = {
.fifo_size = 16,
.segctl_init_val = 0x0333F000,
.txf_sts_tx_bytes = GENMASK(4, 0),
.rxf_sts_rx_bytes = GENMASK(4, 0),
.rxf_ctl_last_pec = BIT(5),
};
static const struct npcm_i2c_data npxm8xx_i2c_data = {
.fifo_size = 32,
.segctl_init_val = 0x9333F000,
.txf_sts_tx_bytes = GENMASK(5, 0),
.rxf_sts_rx_bytes = GENMASK(5, 0),
.rxf_ctl_last_pec = BIT(7),
};
/* Status of one I2C module */
struct npcm_i2c {
struct i2c_adapter adap;
struct device *dev;
unsigned char __iomem *reg;
const struct npcm_i2c_data *data;
spinlock_t lock; /* IRQ synchronization */
struct completion cmd_complete;
int cmd_err;
struct i2c_msg *msgs;
int msgs_num;
int num;
u32 apb_clk;
struct i2c_bus_recovery_info rinfo;
enum i2c_state state;
enum i2c_oper operation;
enum i2c_mode master_or_slave;
enum i2c_state_ind stop_ind;
u8 dest_addr;
u8 *rd_buf;
u16 rd_size;
u16 rd_ind;
u8 *wr_buf;
u16 wr_size;
u16 wr_ind;
bool fifo_use;
u16 PEC_mask; /* PEC bit mask per slave address */
bool PEC_use;
bool read_block_use;
unsigned long int_time_stamp;
unsigned long bus_freq; /* in Hz */
#if IS_ENABLED(CONFIG_I2C_SLAVE)
u8 own_slave_addr;
struct i2c_client *slave;
int slv_rd_size;
int slv_rd_ind;
int slv_wr_size;
int slv_wr_ind;
u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE];
u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE];
#endif
u64 ber_cnt;
u64 rec_succ_cnt;
u64 rec_fail_cnt;
u64 nack_cnt;
u64 timeout_cnt;
u64 tx_complete_cnt;
};
static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
enum i2c_bank bank)
{
u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
if (bank == I2C_BANK_0)
i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
else
i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
}
static void npcm_i2c_init_params(struct npcm_i2c *bus)
{
bus->stop_ind = I2C_NO_STATUS_IND;
bus->rd_size = 0;
bus->wr_size = 0;
bus->rd_ind = 0;
bus->wr_ind = 0;
bus->read_block_use = false;
bus->int_time_stamp = 0;
bus->PEC_use = false;
bus->PEC_mask = 0;
#if IS_ENABLED(CONFIG_I2C_SLAVE)
if (bus->slave)
bus->master_or_slave = I2C_SLAVE;
#endif
}
static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
{
iowrite8(data, bus->reg + NPCM_I2CSDA);
}
static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
{
return ioread8(bus->reg + NPCM_I2CSDA);
}
static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
{
struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
}
static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
{
struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
}
static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
{
if (bus->operation == I2C_READ_OPER)
return bus->rd_ind;
if (bus->operation == I2C_WRITE_OPER)
return bus->wr_ind;
return 0;
}
/* quick protocol (just address) */
static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
{
return bus->wr_size == 0 && bus->rd_size == 0;
}
static void npcm_i2c_disable(struct npcm_i2c *bus)
{
u8 i2cctl2;
#if IS_ENABLED(CONFIG_I2C_SLAVE)
int i;
/* Slave addresses removal */
for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++)
iowrite8(0, bus->reg + npcm_i2caddr[i]);
#endif
/* Disable module */
i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
bus->state = I2C_DISABLE;
}
static void npcm_i2c_enable(struct npcm_i2c *bus)
{
u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
bus->state = I2C_IDLE;
}
/* enable\disable end of busy (EOB) interrupts */
static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
{
u8 val;
/* Clear EO_BUSY pending bit: */
val = ioread8(bus->reg + NPCM_I2CCST3);
val = val | NPCM_I2CCST3_EO_BUSY;
iowrite8(val, bus->reg + NPCM_I2CCST3);
val = ioread8(bus->reg + NPCM_I2CCTL1);
val &= ~NPCM_I2CCTL1_RWS;
if (enable)
val |= NPCM_I2CCTL1_EOBINTE;
else
val &= ~NPCM_I2CCTL1_EOBINTE;
iowrite8(val, bus->reg + NPCM_I2CCTL1);
}
static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
{
u8 tx_fifo_sts;
tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
/* check if TX FIFO is not empty */
if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0)
return false;
/* check if TX FIFO status bit is set: */
return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
}
static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
{
u8 rx_fifo_sts;
rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
/* check if RX FIFO is not empty: */
if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0)
return false;
/* check if rx fifo full status is set: */
return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
}
static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
{
u8 val;
val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
}
static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
{
u8 val;
val = ioread8(bus->reg + NPCM_I2CTXF_STS);
val = val | NPCM_I2CTXF_STS_TX_THST;
iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
}
static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
{
u8 val;
val = ioread8(bus->reg + NPCM_I2CRXF_STS);
val = val | NPCM_I2CRXF_STS_RX_THST;
iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
}
static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
{
u8 val;
val = ioread8(bus->reg + NPCM_I2CCTL1);
val &= ~NPCM_I2CCTL1_RWS;
if (enable)
val |= NPCM_I2CCTL1_INTEN;
else
val &= ~NPCM_I2CCTL1_INTEN;
iowrite8(val, bus->reg + NPCM_I2CCTL1);
}
static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
{
u8 val;
val = ioread8(bus->reg + NPCM_I2CCTL1);
val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
val |= NPCM_I2CCTL1_START;
iowrite8(val, bus->reg + NPCM_I2CCTL1);
}
static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
{
u8 val;
/*
* override HW issue: I2C may fail to supply stop condition in Master
* Write operation.
* Need to delay at least 5 us from the last int, before issueing a stop
*/
udelay(10); /* function called from interrupt, can't sleep */
val = ioread8(bus->reg + NPCM_I2CCTL1);
val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
val |= NPCM_I2CCTL1_STOP;
iowrite8(val, bus->reg + NPCM_I2CCTL1);
if (!bus->fifo_use)
return;
npcm_i2c_select_bank(bus, I2C_BANK_1);
if (bus->operation == I2C_READ_OPER)
npcm_i2c_clear_rx_fifo(bus);
else
npcm_i2c_clear_tx_fifo(bus);
npcm_i2c_clear_fifo_int(bus);
iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
}
static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
{
u8 val;
val = ioread8(bus->reg + NPCM_I2CCTL1);
val &= ~NPCM_I2CCTL1_RWS;
if (stall)
val |= NPCM_I2CCTL1_STASTRE;
else
val &= ~NPCM_I2CCTL1_STASTRE;
iowrite8(val, bus->reg + NPCM_I2CCTL1);
}
static inline void npcm_i2c_nack(struct npcm_i2c *bus)
{
u8 val;
val = ioread8(bus->reg + NPCM_I2CCTL1);
val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
val |= NPCM_I2CCTL1_ACK;
iowrite8(val, bus->reg + NPCM_I2CCTL1);
}
static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
{
u8 val;
/* Clear NEGACK, STASTR and BER bits */
val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
iowrite8(val, bus->reg + NPCM_I2CST);
}
#if IS_ENABLED(CONFIG_I2C_SLAVE)
static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
{
u8 i2cctl1;
/* enable interrupt on slave match: */
i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
i2cctl1 &= ~NPCM_I2CCTL1_RWS;
if (enable)
i2cctl1 |= NPCM_I2CCTL1_NMINTE;
else
i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
}
static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
u8 addr, bool enable)
{
u8 i2cctl1;
u8 i2cctl3;
u8 sa_reg;
sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
if (addr_type == I2C_GC_ADDR) {
i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
if (enable)
i2cctl1 |= NPCM_I2CCTL1_GCMEN;
else
i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
return 0;
} else if (addr_type == I2C_ARP_ADDR) {
i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
if (enable)
i2cctl3 |= I2CCTL3_ARPMEN;
else
i2cctl3 &= ~I2CCTL3_ARPMEN;
iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
return 0;
}
if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
if (addr_type >= I2C_ARP_ADDR)
return -EFAULT;
/* Set and enable the address */
iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
npcm_i2c_slave_int_enable(bus, enable);
return 0;
}
#endif
static void npcm_i2c_reset(struct npcm_i2c *bus)
{
/*
* Save I2CCTL1 relevant bits. It is being cleared when the module
* is disabled.
*/
u8 i2cctl1;
#if IS_ENABLED(CONFIG_I2C_SLAVE)
u8 addr;
#endif
i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
npcm_i2c_disable(bus);
npcm_i2c_enable(bus);
/* Restore NPCM_I2CCTL1 Status */
i2cctl1 &= ~NPCM_I2CCTL1_RWS;
iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
/* Clear BB (BUS BUSY) bit */
iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
iowrite8(0xFF, bus->reg + NPCM_I2CST);
/* Clear and disable EOB */
npcm_i2c_eob_int(bus, false);
/* Clear all fifo bits: */
iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
#if IS_ENABLED(CONFIG_I2C_SLAVE)
if (bus->slave) {
addr = bus->slave->addr;
npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
}
#endif
/* Clear status bits for spurious interrupts */
npcm_i2c_clear_master_status(bus);
bus->state = I2C_IDLE;
}
static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
{
return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
}
static void npcm_i2c_callback(struct npcm_i2c *bus,
enum i2c_state_ind op_status, u16 info)
{
struct i2c_msg *msgs;
int msgs_num;
bool do_complete = false;
msgs = bus->msgs;
msgs_num = bus->msgs_num;
/*
* check that transaction was not timed-out, and msgs still
* holds a valid value.
*/
if (!msgs)
return;
if (completion_done(&bus->cmd_complete))
return;
switch (op_status) {
case I2C_MASTER_DONE_IND:
bus->cmd_err = bus->msgs_num;
if (bus->tx_complete_cnt < ULLONG_MAX)
bus->tx_complete_cnt++;
fallthrough;
case I2C_BLOCK_BYTES_ERR_IND:
/* Master tx finished and all transmit bytes were sent */
if (bus->msgs) {
if (msgs[0].flags & I2C_M_RD)
msgs[0].len = info;
else if (msgs_num == 2 &&
msgs[1].flags & I2C_M_RD)
msgs[1].len = info;
}
do_complete = true;
break;
case I2C_NACK_IND:
/* MASTER transmit got a NACK before tx all bytes */
bus->cmd_err = -ENXIO;
do_complete = true;
break;
case I2C_BUS_ERR_IND:
/* Bus error */
bus->cmd_err = -EAGAIN;
do_complete = true;
break;
case I2C_WAKE_UP_IND:
/* I2C wake up */
break;
default:
break;
}
bus->operation = I2C_NO_OPER;
#if IS_ENABLED(CONFIG_I2C_SLAVE)
if (bus->slave)
bus->master_or_slave = I2C_SLAVE;
#endif
if (do_complete)
complete(&bus->cmd_complete);
}
static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
{
if (bus->operation == I2C_WRITE_OPER)
return (bus->data->txf_sts_tx_bytes &
ioread8(bus->reg + NPCM_I2CTXF_STS));
if (bus->operation == I2C_READ_OPER)
return (bus->data->rxf_sts_rx_bytes &
ioread8(bus->reg + NPCM_I2CRXF_STS));
return 0;
}
static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
{
u8 size_free_fifo;
/*
* Fill the FIFO, while the FIFO is not full and there are more bytes
* to write
*/
size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
while (max_bytes-- && size_free_fifo) {
if (bus->wr_ind < bus->wr_size)
npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
else
npcm_i2c_wr_byte(bus, 0xFF);
size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
}
}
/*
* npcm_i2c_set_fifo:
* configure the FIFO before using it. If nread is -1 RX FIFO will not be
* configured. same for nwrite
*/
static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
{
u8 rxf_ctl = 0;
if (!bus->fifo_use)
return;
npcm_i2c_select_bank(bus, I2C_BANK_1);
npcm_i2c_clear_tx_fifo(bus);
npcm_i2c_clear_rx_fifo(bus);
/* configure RX FIFO */
if (nread > 0) {
rxf_ctl = min_t(int, nread, bus->data->fifo_size);
/* set LAST bit. if LAST is set next FIFO packet is nacked */
if (nread <= bus->data->fifo_size)
rxf_ctl |= bus->data->rxf_ctl_last_pec;
/*
* if we are about to read the first byte in blk rd mode,
* don't NACK it. If slave returns zero size HW can't NACK
* it immediately, it will read extra byte and then NACK.
*/
if (bus->rd_ind == 0 && bus->read_block_use) {
/* set fifo to read one byte, no last: */
rxf_ctl = 1;
}
/* set fifo size: */
iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
}
/* configure TX FIFO */
if (nwrite > 0) {
if (nwrite > bus->data->fifo_size)
/* data to send is more then FIFO size. */
iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL);
else
iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
npcm_i2c_clear_tx_fifo(bus);
}
}
static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
{
u8 data;
while (bytes_in_fifo--) {
data = npcm_i2c_rd_byte(bus);
if (bus->rd_ind < bus->rd_size)
bus->rd_buf[bus->rd_ind++] = data;
}
}
static void npcm_i2c_master_abort(struct npcm_i2c *bus)
{
/* Only current master is allowed to issue a stop condition */
if (!npcm_i2c_is_master(bus))
return;
npcm_i2c_eob_int(bus, true);
npcm_i2c_master_stop(bus);
npcm_i2c_clear_master_status(bus);
}
#if IS_ENABLED(CONFIG_I2C_SLAVE)
static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
{
u8 slave_add;
if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
return slave_add;
}
static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
{
int i;
/* Set the enable bit */
slave_add |= 0x80;
for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) {
if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
iowrite8(0, bus->reg + npcm_i2caddr[i]);
}
return 0;
}
static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
{
/*
* Fill the FIFO, while the FIFO is not full and there are more bytes
* to write
*/
npcm_i2c_clear_fifo_int(bus);
npcm_i2c_clear_tx_fifo(bus);
iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) {
if (bus->slv_wr_size <= 0)
break;
bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
bus->slv_wr_ind++;
bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
bus->slv_wr_size--;
}
}
static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
{
u8 data;
if (!bus->slave)
return;
while (bytes_in_fifo--) {
data = npcm_i2c_rd_byte(bus);
bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1);
bus->slv_rd_buf[bus->slv_rd_ind] = data;
bus->slv_rd_ind++;
/* 1st byte is length in block protocol: */
if (bus->slv_rd_ind == 1 && bus->read_block_use)
bus->slv_rd_size = data + bus->PEC_use + 1;
}
}
static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
{
int i;
u8 value;
int ind;
int ret = bus->slv_wr_ind;
/* fill a cyclic buffer */
for (i = 0; i < bus->data->fifo_size; i++) {
if (bus->slv_wr_size >= bus->data->fifo_size)
break;
if (bus->state == I2C_SLAVE_MATCH) {
i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
bus->state = I2C_OPER_STARTED;
} else {
i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
}
ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1);
bus->slv_wr_buf[ind] = value;
bus->slv_wr_size++;
}
return bus->data->fifo_size - ret;
}
static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
{
int i;
for (i = 0; i < bus->slv_rd_ind; i++)
i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
&bus->slv_rd_buf[i]);
/*
* once we send bytes up, need to reset the counter of the wr buf
* got data from master (new offset in device), ignore wr fifo:
*/
if (bus->slv_rd_ind) {
bus->slv_wr_size = 0;
bus->slv_wr_ind = 0;
}
bus->slv_rd_ind = 0;
bus->slv_rd_size = bus->adap.quirks->max_read_len;
npcm_i2c_clear_fifo_int(bus);
npcm_i2c_clear_rx_fifo(bus);
}
static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
u8 *read_data)
{
bus->state = I2C_OPER_STARTED;
bus->operation = I2C_READ_OPER;
bus->slv_rd_size = nread;
bus->slv_rd_ind = 0;
iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
npcm_i2c_clear_tx_fifo(bus);
npcm_i2c_clear_rx_fifo(bus);
}
static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
u8 *write_data)
{
if (nwrite == 0)
return;
bus->operation = I2C_WRITE_OPER;
/* get the next buffer */
npcm_i2c_slave_get_wr_buf(bus);
npcm_i2c_write_fifo_slave(bus, nwrite);
}
/*
* npcm_i2c_slave_wr_buf_sync:
* currently slave IF only supports single byte operations.
* in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes
* at a time, pack them in buffer, and then transmit them all together
* to the FIFO and onward to the bus.