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x variable get colored differently #2

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DidierMalenfant opened this issue Apr 8, 2023 · 6 comments
Closed

x variable get colored differently #2

DidierMalenfant opened this issue Apr 8, 2023 · 6 comments
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@DidierMalenfant
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This is a bit above my pay grade because I'm terrible at regex but it seems that x gets caught by some syntax rule and ends up with a different color than y on the following screenshot:

Screenshot 2023-04-04 at 13 33 51

@tsalvo
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tsalvo commented Apr 8, 2023

Thanks for reporting this. I think I can take a look sometime in the next few days, and try to take out some of the Verilog syntax highlighting rules to see which one is causing it to mistakenly highlight.

@tsalvo tsalvo self-assigned this Apr 8, 2023
@tsalvo tsalvo added the bug Something isn't working label Apr 8, 2023
@tsalvo
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tsalvo commented Apr 8, 2023

@DidierMalenfant

Thinking back to why this happens, I think this is the reason.

Four State Data Types
The logic, reg, and wire data types can take one of four values: 0, 1, X, Z, where X is unknown, and Z is high impedance.

There are some regex rules below for values that take X and Z into account, but... I'm thinking it might be better to remove xXzZ from them, because it's not easy to know the context of whether they are just being used as names, or for this very specific reason.

<scope name="verilog.value.number.hex">
    <expression>(\b|')h[0-9a-fA-FxXzZ]+(\b|;)</expression>
</scope>
<scope name="verilog.value.number.boolean">
    <expression>(\b|')b[0-1xXzZ]+(\b|;)</expression>
</scope>
<scope name="verilog.value.number.dec">
    <expression>(\b|'d)[0-9xXzZ]+(\b|;)</expression>
</scope>
<scope name="objc.value.number">
    <expression>(\b|')[0-9xXzZ]+(\b|;)</expression>
</scope>

I'll give this some more thought, but I'm pretty sure that if I remove xXzZ from these rules, it will fix the issue.

@tsalvo
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tsalvo commented Apr 8, 2023

Screenshot 2023-04-08 at 1 25 45 PM

Actually, just removing xXzZ has downsides, because it will prevent a value such as 32'hF8xxxxxx from highlighting as a value:

// for core_bridge_cmd
    32'hF8xxxxxx: begin
        bridge_rd_data <= cmd_bridge_rd_data;

I might need to brush up on my regex and update those value rules to exclude something that starts with x or z.

@tsalvo
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tsalvo commented Apr 11, 2023

@DidierMalenfant I think I have a fix for this:
#5

Still testing it out, but let me know if you have a chance to try this branch out. No worries if not

@DidierMalenfant
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Seems to work fine for me.

@tsalvo
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tsalvo commented Apr 12, 2023

Fixed in 0.0.4

@tsalvo tsalvo closed this as completed Apr 12, 2023
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