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x variable get colored differently #2
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Thanks for reporting this. I think I can take a look sometime in the next few days, and try to take out some of the Verilog syntax highlighting rules to see which one is causing it to mistakenly highlight. |
Thinking back to why this happens, I think this is the reason.
There are some regex rules below for values that take X and Z into account, but... I'm thinking it might be better to remove
I'll give this some more thought, but I'm pretty sure that if I remove |
Actually, just removing
I might need to brush up on my regex and update those value rules to exclude something that starts with |
@DidierMalenfant I think I have a fix for this: Still testing it out, but let me know if you have a chance to try this branch out. No worries if not |
Seems to work fine for me. |
Fixed in 0.0.4 |
This is a bit above my pay grade because I'm terrible at regex but it seems that
x
gets caught by some syntax rule and ends up with a different color thany
on the following screenshot:The text was updated successfully, but these errors were encountered: