Guidelines

This repository contains code for 5 stage pipelined 32-bit processor using RISC-V Instruction Set Architecture (ISA).

Compilation and Simulation process is explained below:

Compilation

RTL can be compiled with the command:

vlog names_of_all_system_verilog_files

or simply:

vlog *.sv

Compilation creates a work folder in your current working directory in which all the files generated after compilation are stored.

The compiled RTL can be simulated with command:

vsim -c name_of_toplevel_module -do "run -all"

Simulation creates a .vcd file. This files contains all the simulation behaviour of design.

To view the waveform of the design run the command:

gtkwave dumpfile_name.vcd

Here dumpfile_name will be processor.vcd

This opens a waveform window. Pull the required signals in the waveform and verify the behaviour of the design.

Name		Name	Last commit message	Last commit date
Latest commit History 56 Commits
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
alu.sv		alu.sv
br_cond.sv		br_cond.sv
compile.bat		compile.bat
controller.sv		controller.sv
csr_reg.mem		csr_reg.mem
csr_reg.sv		csr_reg.sv
csr_reg_out.mem		csr_reg_out.mem
data_mem.sv		data_mem.sv
dm.mem		dm.mem
dm_out.mem		dm_out.mem
imm_gen.sv		imm_gen.sv
inst.mem		inst.mem
inst_dec.sv		inst_dec.sv
inst_mem.sv		inst_mem.sv
mux_2x1.sv		mux_2x1.sv
mux_4x1.sv		mux_4x1.sv
pc.sv		pc.sv
processor.sv		processor.sv
reg_file.sv		reg_file.sv
rf.mem		rf.mem
rf_out.mem		rf_out.mem
riscv-privileged-v1.10.pdf		riscv-privileged-v1.10.pdf
riscv_inst_formats.png		riscv_inst_formats.png
single_cycle_processor.drawio.png		single_cycle_processor.drawio.png
tb_processor.sv		tb_processor.sv
timer.sv		timer.sv