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RVA.core_desc
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RVA.core_desc
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import "RISCVBase.core_desc"
InstructionSet RV32A extends RISCVBase {
instructions {
LRW {
encoding: 5'b00010 :: aq[0:0] :: rl[0:0] :: 5'b00000 :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(aq)}, {name(rl)}";
behavior: if ((rd % RFS) != 0) {
unsigned<XLEN> offs = X[rs1 % RFS];
X[rd % RFS] = (signed<XLEN>)((signed<32>)MEM[offs]);
RES[offs] = -1;
}
}
SCW {
encoding: 5'b00011 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}, {name(aq)}, {name(rl)}";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
unsigned<32> res1 = RES[offs];
if (res1 != 0)
MEM[offs] = X[rs2 % RFS];
if ((rd % RFS) != 0)
X[rd % RFS] = res1 ? 0 : 1;
}
}
AMOSWAPW {
encoding: 5'b00001 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
if ((rd % RFS) != 0) X[rd % RFS] = (signed<XLEN>)((signed<32>)MEM[offs]);
MEM[offs] = (signed<32>)X[rs2 % RFS];
}
}
AMOADDW {
encoding: 5'b00000 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<32> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res1;
unsigned<32> res2 = res1 + X[rs2 % RFS];
MEM[offs] = res2;
}
}
AMOXORW {
encoding: 5'b00100 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<32> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res1;
unsigned<32> res2 = res1 ^ X[rs2 % RFS];
MEM[offs] = res2;
}
}
AMOANDW {
encoding: 5'b01100 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<32> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res1;
unsigned<32> res2 = res1 & X[rs2 % RFS];
MEM[offs] = res2;
}
}
AMOORW {
encoding: 5'b01000 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<32> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res1;
unsigned<32> res2 = res1 | X[rs2 % RFS];
MEM[offs] = res2;
}
}
AMOMINW {
encoding: 5'b10000 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<32> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res1;
unsigned<32> res2 = res1 > (signed<32>)X[rs2 % RFS] ? X[rs2 % RFS] : res1;
MEM[offs] = res2;
}
}
AMOMAXW {
encoding: 5'b10100 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<32> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res1;
unsigned<32> res2 = res1 < (signed<32>)X[rs2 % RFS] ? X[rs2 % RFS] : res1;
MEM[offs] = res2;
}
}
AMOMINUW {
encoding: 5'b11000 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
unsigned<32> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = (signed<32>)res1;
unsigned<32> res2 = res1 > (unsigned<32>)X[rs2 % RFS] ? X[rs2 % RFS] : res1;
MEM[offs] = res2;
}
}
AMOMAXUW {
encoding: 5'b11100 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
unsigned<32> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = (signed<32>)res1;
unsigned<32> res2 = res1 < (unsigned<32>)X[rs2 % RFS] ? X[rs2 % RFS] : res1;
MEM[offs] = res2;
}
}
}
}
InstructionSet RV64A extends RV32A {
instructions {
LRD {
encoding: 5'b00010 :: aq[0:0] :: rl[0:0] :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}";
behavior: {
if ((rd % RFS) != 0) {
unsigned<XLEN> offs = X[rs1 % RFS];
X[rd % RFS] = (signed<XLEN>)((signed<64>)MEM[offs]);
RES[offs] = -1;
}
}
}
SCD {
encoding: 5'b00011 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
unsigned<64> res = RES[offs];
if (res != 0)
MEM[offs] = X[rs2 % RFS];
if ((rd % RFS) != 0)
X[rd % RFS] = res1 ? 0 : 1;
}
}
AMOSWAPD {
encoding: 5'b00001 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
if ((rd % RFS) != 0) X[rd % RFS] = (signed<XLEN>)((signed<64>)MEM[offs]);
MEM[offs] = (signed<64>)X[rs2 % RFS];
}
}
AMOADDD {
encoding: 5'b00000 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<64> res = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<64> res2 = res + X[rs2 % RFS];
MEM[offs] = res2;
}
}
AMOXORD {
encoding: 5'b00100 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<64> res = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<64> res2 = res ^ X[rs2 % RFS];
MEM[offs] = res2;
}
}
AMOANDD {
encoding: 5'b01100 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<64> res = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<64> res2 = res & X[rs2 % RFS];
MEM[offs] = res2;
}
}
AMOORD {
encoding: 5'b01000 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<64> res = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<64> res2 = res | X[rs2 % RFS];
MEM[offs] = res2;
}
}
AMOMIND {
encoding: 5'b10000 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<64> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res1;
unsigned<64> res2 = res1 > (signed<64>)X[rs2 % RFS] ? X[rs2 % RFS] : res1;
MEM[offs] = res2;
}
}
AMOMAXD {
encoding: 5'b10100 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
signed<64> res = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<64> res2 = res < (signed<64>)X[rs2 % RFS] ? X[rs2 % RFS] : res;
MEM[offs] = res2;
}
}
AMOMINUD {
encoding: 5'b11000 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
unsigned<64> res = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = (signed<64>)res;
unsigned<64> res2 = res > X[rs2 % RFS] ? X[rs2 % RFS] : res;
MEM[offs] = res2;
}
}
AMOMAXUD {
encoding: 5'b11100 :: aq[0:0] :: rl[0:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101111;
assembly: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu = {aq},rel = {rl})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS];
unsigned<64> res1 = MEM[offs];
if ((rd % RFS) != 0) X[rd % RFS] = (signed<64>)res1;
unsigned<64> res2 = res1 < X[rs2 % RFS] ? X[rs2 % RFS] : res1;
MEM[offs] = res2;
}
}
}
}