/
asmz.go
4791 lines (4504 loc) · 168 KB
/
asmz.go
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// Based on cmd/internal/obj/ppc64/asm9.go.
//
// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
// Portions Copyright © 1997-1999 Vita Nuova Limited
// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
// Portions Copyright © 2004,2006 Bruce Ellis
// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
// Portions Copyright © 2009 The Go Authors. All rights reserved.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
package s390x
import (
"cmd/internal/obj"
"cmd/internal/objabi"
"log"
"math"
"sort"
)
// ctxtz holds state while assembling a single function.
// Each function gets a fresh ctxtz.
// This allows for multiple functions to be safely concurrently assembled.
type ctxtz struct {
ctxt *obj.Link
newprog obj.ProgAlloc
cursym *obj.LSym
autosize int32
instoffset int64
pc int64
}
// instruction layout.
const (
funcAlign = 16
)
type Optab struct {
as obj.As // opcode
a1 uint8 // From
a2 uint8 // Reg
a3 uint8 // From3
a4 uint8 // To
type_ int8
param int16 // REGSP for auto variables
}
var optab = []Optab{
// instruction, From, Reg, From3, To, type, param
Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0},
Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0},
// move register
Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0},
Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0},
// load constant
Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP},
Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP},
Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP},
Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0},
// store constant
Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP},
Optab{AMOVD, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0},
Optab{AMOVD, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0},
Optab{AMOVW, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0},
Optab{AMOVW, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0},
Optab{AMOVWZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0},
Optab{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0},
Optab{AMOVB, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0},
Optab{AMOVB, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0},
Optab{AMOVBZ, C_SCON, C_NONE, C_NONE, C_LOREG, 72, 0},
Optab{AMOVBZ, C_ADDCON, C_NONE, C_NONE, C_LOREG, 72, 0},
// store
Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0},
Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0},
// load
Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP},
Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0},
Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0},
// interlocked load and op
Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0},
// integer arithmetic
Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0},
Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0},
Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0},
Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0},
Optab{AADD, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0},
Optab{AADD, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP},
Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 21, 0},
Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 21, 0},
Optab{ASUB, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0},
Optab{ASUB, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP},
Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0},
Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0},
Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0},
Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0},
Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0},
Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0},
Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0},
Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0},
// integer logical
Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0},
Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0},
Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0},
Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0},
Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP},
Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0},
Optab{AANDW, C_REG, C_NONE, C_NONE, C_REG, 6, 0},
Optab{AANDW, C_LCON, C_NONE, C_NONE, C_REG, 24, 0},
Optab{AANDW, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0},
Optab{AANDW, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP},
Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0},
Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0},
Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0},
Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0},
// compare and swap
Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0},
// floating point
Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0},
Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0},
Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0},
Optab{AFMADD, C_FREG, C_FREG, C_NONE, C_FREG, 34, 0},
Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0},
Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP},
Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0},
Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0},
Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP},
Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0},
Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0},
Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0},
Optab{ALDGR, C_REG, C_NONE, C_NONE, C_FREG, 81, 0},
Optab{ALGDR, C_FREG, C_NONE, C_NONE, C_REG, 81, 0},
Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0},
Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0},
Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0},
Optab{ACPSDR, C_FREG, C_FREG, C_NONE, C_FREG, 49, 0},
Optab{ALTDBR, C_FREG, C_NONE, C_NONE, C_FREG, 50, 0},
Optab{ATCDB, C_FREG, C_NONE, C_NONE, C_SCON, 51, 0},
// load symbol address (plus offset)
Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0},
Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0},
Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0},
Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0},
// system call
Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0},
Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0},
// branch
Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0},
Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0},
Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0},
Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0},
Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0},
Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0},
Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0},
Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0},
Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0},
Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0},
Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0},
Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0},
// move on condition
Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0},
// find leftmost one
Optab{AFLOGR, C_REG, C_NONE, C_NONE, C_REG, 8, 0},
// population count
Optab{APOPCNT, C_REG, C_NONE, C_NONE, C_REG, 9, 0},
// compare
Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0},
Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0},
Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0},
Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0},
Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0},
Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0},
// test under mask
Optab{ATMHH, C_REG, C_NONE, C_NONE, C_ANDCON, 91, 0},
// 32-bit access registers
Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0},
Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0},
Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0},
Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0},
// macros
Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0},
Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP},
// load/store multiple
Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0},
Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP},
Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0},
Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP},
// bytes
Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0},
Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0},
Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0},
Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0},
// fast synchronization
Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 80, 0},
// store clock
Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP},
Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0},
// storage and storage
Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LOREG, 84, 0},
Optab{AMVC, C_SCON, C_NONE, C_LOREG, C_LAUTO, 84, REGSP},
Optab{AMVC, C_SCON, C_NONE, C_LAUTO, C_LAUTO, 84, REGSP},
// address
Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0},
Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0},
Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0},
Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP},
Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0},
// misc
Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0},
Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0},
Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0},
Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0},
Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0},
// vector instructions
// VRX store
Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0},
Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP},
Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SOREG, 100, 0},
Optab{AVSTEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 100, REGSP},
// VRX load
Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0},
Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP},
Optab{AVLEG, C_SCON, C_NONE, C_SOREG, C_VREG, 101, 0},
Optab{AVLEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 101, REGSP},
// VRV scatter
Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SOREG, 102, 0},
Optab{AVSCEG, C_SCON, C_VREG, C_NONE, C_SAUTO, 102, REGSP},
// VRV gather
Optab{AVGEG, C_SCON, C_NONE, C_SOREG, C_VREG, 103, 0},
Optab{AVGEG, C_SCON, C_NONE, C_SAUTO, C_VREG, 103, REGSP},
// VRS element shift/rotate and load gr to/from vr element
Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0},
Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0},
Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0},
Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0},
Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0},
Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0},
Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0},
Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0},
// VRS store multiple
Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0},
Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP},
// VRS load multiple
Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0},
Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP},
// VRS store with length
Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SOREG, 107, 0},
Optab{AVSTL, C_REG, C_VREG, C_NONE, C_SAUTO, 107, REGSP},
// VRS load with length
Optab{AVLL, C_REG, C_NONE, C_SOREG, C_VREG, 108, 0},
Optab{AVLL, C_REG, C_NONE, C_SAUTO, C_VREG, 108, REGSP},
// VRI-a
Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0},
Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0},
Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0},
Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0},
Optab{AVLEIG, C_SCON, C_NONE, C_ADDCON, C_VREG, 109, 0},
Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0},
// VRI-b generate mask
Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0},
// VRI-c replicate
Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0},
// VRI-d element rotate and insert under mask and
// shift left double by byte
Optab{AVERIMG, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0},
Optab{AVSLDB, C_SCON, C_VREG, C_VREG, C_VREG, 112, 0},
// VRI-d fp test data class immediate
Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0},
// VRR-a load reg
Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0},
// VRR-a compare
Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0},
// VRR-b
Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0},
Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0},
Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0},
// VRR-c
Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0},
Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0},
Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0},
Optab{AVPDI, C_SCON, C_VREG, C_VREG, C_VREG, 123, 0},
// VRR-c shifts
Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0},
Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0},
// VRR-d
// 2 3 1 4
Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0},
// VRR-e
Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0},
// VRR-f
Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0},
}
var oprange [ALAST & obj.AMask][]Optab
var xcmp [C_NCLASS][C_NCLASS]bool
func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
p := cursym.Func.Text
if p == nil || p.Link == nil { // handle external functions and ELF section symbols
return
}
if oprange[AORW&obj.AMask] == nil {
ctxt.Diag("s390x ops not initialized, call s390x.buildop first")
}
c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
buffer := make([]byte, 0)
changed := true
loop := 0
for changed {
if loop > 100 {
c.ctxt.Diag("stuck in spanz loop")
break
}
changed = false
buffer = buffer[:0]
c.cursym.R = make([]obj.Reloc, 0)
for p := c.cursym.Func.Text; p != nil; p = p.Link {
pc := int64(len(buffer))
if pc != p.Pc {
changed = true
}
p.Pc = pc
c.pc = p.Pc
c.asmout(p, &buffer)
if pc == int64(len(buffer)) {
switch p.As {
case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
// ok
default:
c.ctxt.Diag("zero-width instruction\n%v", p)
}
}
}
loop++
}
c.cursym.Size = int64(len(buffer))
if c.cursym.Size%funcAlign != 0 {
c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign)
}
c.cursym.Grow(c.cursym.Size)
copy(c.cursym.P, buffer)
}
func isint32(v int64) bool {
return int64(int32(v)) == v
}
func isuint32(v uint64) bool {
return uint64(uint32(v)) == v
}
func (c *ctxtz) aclass(a *obj.Addr) int {
switch a.Type {
case obj.TYPE_NONE:
return C_NONE
case obj.TYPE_REG:
if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
return C_REG
}
if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
return C_FREG
}
if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
return C_AREG
}
if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
return C_VREG
}
return C_GOK
case obj.TYPE_MEM:
switch a.Name {
case obj.NAME_EXTERN,
obj.NAME_STATIC:
if a.Sym == nil {
// must have a symbol
break
}
c.instoffset = a.Offset
if a.Sym.Type == objabi.STLSBSS {
if c.ctxt.Flag_shared {
return C_TLS_IE // initial exec model
}
return C_TLS_LE // local exec model
}
return C_ADDR
case obj.NAME_GOTREF:
return C_GOTADDR
case obj.NAME_AUTO:
if a.Reg == REGSP {
// unset base register for better printing, since
// a.Offset is still relative to pseudo-SP.
a.Reg = obj.REG_NONE
}
c.instoffset = int64(c.autosize) + a.Offset
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SAUTO
}
return C_LAUTO
case obj.NAME_PARAM:
if a.Reg == REGSP {
// unset base register for better printing, since
// a.Offset is still relative to pseudo-FP.
a.Reg = obj.REG_NONE
}
c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SAUTO
}
return C_LAUTO
case obj.NAME_NONE:
c.instoffset = a.Offset
if c.instoffset == 0 {
return C_ZOREG
}
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SOREG
}
return C_LOREG
}
return C_GOK
case obj.TYPE_TEXTSIZE:
return C_TEXTSIZE
case obj.TYPE_FCONST:
if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
return C_ZCON
}
c.ctxt.Diag("cannot handle the floating point constant %v", a.Val)
case obj.TYPE_CONST,
obj.TYPE_ADDR:
switch a.Name {
case obj.NAME_NONE:
c.instoffset = a.Offset
if a.Reg != 0 {
if -BIG <= c.instoffset && c.instoffset <= BIG {
return C_SACON
}
if isint32(c.instoffset) {
return C_LACON
}
return C_DACON
}
case obj.NAME_EXTERN,
obj.NAME_STATIC:
s := a.Sym
if s == nil {
return C_GOK
}
c.instoffset = a.Offset
return C_SYMADDR
case obj.NAME_AUTO:
if a.Reg == REGSP {
// unset base register for better printing, since
// a.Offset is still relative to pseudo-SP.
a.Reg = obj.REG_NONE
}
c.instoffset = int64(c.autosize) + a.Offset
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SACON
}
return C_LACON
case obj.NAME_PARAM:
if a.Reg == REGSP {
// unset base register for better printing, since
// a.Offset is still relative to pseudo-FP.
a.Reg = obj.REG_NONE
}
c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
if c.instoffset >= -BIG && c.instoffset < BIG {
return C_SACON
}
return C_LACON
default:
return C_GOK
}
if c.instoffset == 0 {
return C_ZCON
}
if c.instoffset >= 0 {
if c.instoffset <= 0x7fff {
return C_SCON
}
if c.instoffset <= 0xffff {
return C_ANDCON
}
if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */
return C_UCON
}
if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
return C_LCON
}
return C_DCON
}
if c.instoffset >= -0x8000 {
return C_ADDCON
}
if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
return C_UCON
}
if isint32(c.instoffset) {
return C_LCON
}
return C_DCON
case obj.TYPE_BRANCH:
return C_SBRA
}
return C_GOK
}
func (c *ctxtz) oplook(p *obj.Prog) *Optab {
a1 := int(p.Optab)
if a1 != 0 {
return &optab[a1-1]
}
a1 = int(p.From.Class)
if a1 == 0 {
a1 = c.aclass(&p.From) + 1
p.From.Class = int8(a1)
}
a1--
a3 := C_NONE + 1
if p.GetFrom3() != nil {
a3 = int(p.GetFrom3().Class)
if a3 == 0 {
a3 = c.aclass(p.GetFrom3()) + 1
p.GetFrom3().Class = int8(a3)
}
}
a3--
a4 := int(p.To.Class)
if a4 == 0 {
a4 = c.aclass(&p.To) + 1
p.To.Class = int8(a4)
}
a4--
a2 := C_NONE
if p.Reg != 0 {
if REG_R0 <= p.Reg && p.Reg <= REG_R15 {
a2 = C_REG
} else if REG_V0 <= p.Reg && p.Reg <= REG_V31 {
a2 = C_VREG
} else if REG_F0 <= p.Reg && p.Reg <= REG_F15 {
a2 = C_FREG
} else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 {
a2 = C_AREG
}
}
ops := oprange[p.As&obj.AMask]
c1 := &xcmp[a1]
c2 := &xcmp[a2]
c3 := &xcmp[a3]
c4 := &xcmp[a4]
for i := range ops {
op := &ops[i]
if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] {
p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
return op
}
}
// cannot find a case; abort
c.ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4))
c.ctxt.Diag("prog: %v\n", p)
return nil
}
func cmp(a int, b int) bool {
if a == b {
return true
}
switch a {
case C_DCON:
if b == C_LCON {
return true
}
fallthrough
case C_LCON:
if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
return true
}
case C_ADDCON:
if b == C_ZCON || b == C_SCON {
return true
}
case C_ANDCON:
if b == C_ZCON || b == C_SCON {
return true
}
case C_UCON:
if b == C_ZCON || b == C_SCON {
return true
}
case C_SCON:
if b == C_ZCON {
return true
}
case C_LACON:
if b == C_SACON {
return true
}
case C_LBRA:
if b == C_SBRA {
return true
}
case C_LAUTO:
if b == C_SAUTO {
return true
}
case C_LOREG:
if b == C_ZOREG || b == C_SOREG {
return true
}
case C_SOREG:
if b == C_ZOREG {
return true
}
case C_ANY:
return true
}
return false
}
type ocmp []Optab
func (x ocmp) Len() int {
return len(x)
}
func (x ocmp) Swap(i, j int) {
x[i], x[j] = x[j], x[i]
}
func (x ocmp) Less(i, j int) bool {
p1 := &x[i]
p2 := &x[j]
n := int(p1.as) - int(p2.as)
if n != 0 {
return n < 0
}
n = int(p1.a1) - int(p2.a1)
if n != 0 {
return n < 0
}
n = int(p1.a2) - int(p2.a2)
if n != 0 {
return n < 0
}
n = int(p1.a3) - int(p2.a3)
if n != 0 {
return n < 0
}
n = int(p1.a4) - int(p2.a4)
if n != 0 {
return n < 0
}
return false
}
func opset(a, b obj.As) {
oprange[a&obj.AMask] = oprange[b&obj.AMask]
}
func buildop(ctxt *obj.Link) {
if oprange[AORW&obj.AMask] != nil {
// Already initialized; stop now.
// This happens in the cmd/asm tests,
// each of which re-initializes the arch.
return
}
for i := 0; i < C_NCLASS; i++ {
for n := 0; n < C_NCLASS; n++ {
if cmp(n, i) {
xcmp[i][n] = true
}
}
}
sort.Sort(ocmp(optab))
for i := 0; i < len(optab); i++ {
r := optab[i].as
start := i
for ; i+1 < len(optab); i++ {
if optab[i+1].as != r {
break
}
}
oprange[r&obj.AMask] = optab[start : i+1]
// opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array.
// oprange[] is used by oplook() to find the Optab entry that applies to a given Prog.
switch r {
case AADD:
opset(AADDC, r)
opset(AADDW, r)
opset(AMULLD, r)
opset(AMULLW, r)
case ADIVW:
opset(AADDE, r)
opset(ADIVD, r)
opset(ADIVDU, r)
opset(ADIVWU, r)
opset(AMODD, r)
opset(AMODDU, r)
opset(AMODW, r)
opset(AMODWU, r)
case AMULHD:
opset(AMULHDU, r)
case AMOVBZ:
opset(AMOVH, r)
opset(AMOVHZ, r)
case ALA:
opset(ALAY, r)
case AMVC:
opset(ACLC, r)
opset(AXC, r)
opset(AOC, r)
opset(ANC, r)
case ASTCK:
opset(ASTCKC, r)
opset(ASTCKE, r)
opset(ASTCKF, r)
case ALAAG:
opset(ALAA, r)
opset(ALAAL, r)
opset(ALAALG, r)
opset(ALAN, r)
opset(ALANG, r)
opset(ALAX, r)
opset(ALAXG, r)
opset(ALAO, r)
opset(ALAOG, r)
case ASTMG:
opset(ASTMY, r)
case ALMG:
opset(ALMY, r)
case ABEQ:
opset(ABGE, r)
opset(ABGT, r)
opset(ABLE, r)
opset(ABLT, r)
opset(ABNE, r)
opset(ABVC, r)
opset(ABVS, r)
opset(ABLEU, r)
opset(ABLTU, r)
case ABR:
opset(ABL, r)
case ABC:
opset(ABCL, r)
case AFABS:
opset(AFNABS, r)
opset(ALPDFR, r)
opset(ALNDFR, r)
opset(AFNEG, r)
opset(AFNEGS, r)
opset(ALEDBR, r)
opset(ALDEBR, r)
opset(AFSQRT, r)
opset(AFSQRTS, r)
case AFADD:
opset(AFADDS, r)
opset(AFDIV, r)
opset(AFDIVS, r)
opset(AFSUB, r)
opset(AFSUBS, r)
case AFMADD:
opset(AFMADDS, r)
opset(AFMSUB, r)
opset(AFMSUBS, r)
case AFMUL:
opset(AFMULS, r)
case AFCMPO:
opset(AFCMPU, r)
opset(ACEBR, r)
case AAND:
opset(AOR, r)
opset(AXOR, r)
case AANDW:
opset(AORW, r)
opset(AXORW, r)
case ASLD:
opset(ASRD, r)
opset(ASLW, r)
opset(ASRW, r)
opset(ASRAD, r)
opset(ASRAW, r)
opset(ARLL, r)
opset(ARLLG, r)
case ACSG:
opset(ACS, r)
case ASUB:
opset(ASUBC, r)
opset(ASUBE, r)
opset(ASUBW, r)
case ANEG:
opset(ANEGW, r)
case AFMOVD:
opset(AFMOVS, r)
case AMOVDBR:
opset(AMOVWBR, r)
case ACMP:
opset(ACMPW, r)
case ACMPU:
opset(ACMPWU, r)
case ATMHH:
opset(ATMHL, r)
opset(ATMLH, r)
opset(ATMLL, r)
case ACEFBRA:
opset(ACDFBRA, r)
opset(ACEGBRA, r)
opset(ACDGBRA, r)
opset(ACELFBR, r)
opset(ACDLFBR, r)
opset(ACELGBR, r)
opset(ACDLGBR, r)
case ACFEBRA:
opset(ACFDBRA, r)
opset(ACGEBRA, r)
opset(ACGDBRA, r)
opset(ACLFEBR, r)
opset(ACLFDBR, r)
opset(ACLGEBR, r)
opset(ACLGDBR, r)
case AFIEBR:
opset(AFIDBR, r)
case ACMPBEQ:
opset(ACMPBGE, r)
opset(ACMPBGT, r)
opset(ACMPBLE, r)
opset(ACMPBLT, r)
opset(ACMPBNE, r)
case ACMPUBEQ:
opset(ACMPUBGE, r)
opset(ACMPUBGT, r)
opset(ACMPUBLE, r)
opset(ACMPUBLT, r)
opset(ACMPUBNE, r)
case AMOVDEQ:
opset(AMOVDGE, r)
opset(AMOVDGT, r)
opset(AMOVDLE, r)
opset(AMOVDLT, r)
opset(AMOVDNE, r)