Jai Luthra <j-luthra@ti.com>
The AM62A SoC family is built on the K3 Multicore SoC architecture platform, providing a deep learning accelerator, multi-camera support with ISP, video transcoder and other BOM-saving integrations. The AM62A SoC enables cost-sensitive automotive applications including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set of industrial applications in Factory Automation, Building Automation, Robotics and more.
Some highlights of this SoC are:
- Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
- Cortex-R5F for general-purpose or safety usage.
- Deep Learning Accelerator with Single-core C7x Vector DSP with MMA (up to 1.0GHz).
- Vision Processing Accelerator (VPAC) with a 315MPixel/s ISP (up to 5MP @ 60fps) supporting 16-bit RAW input with RGB-IR separation.
- 4K Video encoder and decoder for HEVC (Level 5.1 High-tier) and H.264 (Level 5.2) supporting upto 240MPixels/s and MJPEG encoder at 416MPixels/s
- Single display with 24-bit RGB parallel (DPI) interface supporting upto 165Mhz pixel clock for 2K resolution.
- Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable).
- 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
- Dedicated Centralized System Controller for Security, Power, and Resource Management.
- Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design.
More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruj16
Platform information:
Below is the pictorial representation of boot flow:
- Here TIFS acts as master and provides all the critical services. R5/A53 requests TIFS to get these services done as shown in the above diagram.
- Setup the environment variables:
Set the variables corresponding to this platform:
$ export UBOOT_CFG_CORTEXR=am62ax_evm_r5_defconfig
$ export UBOOT_CFG_CORTEXA=am62ax_evm_a53_defconfig
$ export TFA_BOARD=lite
$ # we dont use any extra TFA parameters
$ unset TFA_EXTRA_ARGS
$ export OPTEE_PLATFORM=k3-am62ax
$ # we dont use any extra OPTEE parameters
$ unset OPTEE_EXTRA_ARGS- Trusted Firmware-A:
- OP-TEE:
- U-Boot:
- 3.1 R5:
- 3.2 A53:
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC variant (GP, HS-FS, HS-SE) requires a different source for these files.
GP
- tiboot3-am62ax-gp-evm.bin from step 3.1
- tispl.bin_unsigned, u-boot.img_unsigned from step 3.2
HS-FS
- tiboot3-am62ax-hs-fs-evm.bin from step 3.1
- tispl.bin, u-boot.img from step 3.2
HS-SE
- tiboot3-am62ax-hs-evm.bin from step 3.1
- tispl.bin, u-boot.img from step 3.2
- tiboot3.bin
- tispl.bin
Boot Mode pins provide means to select the boot mode and options before the device is powered up. After every POR, they are the main source to populate the Boot Parameter Tables.
The following table shows some common boot modes used on AM62 platform. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruj16 under the Boot Mode Pins section.
Boot Modes| Switch Label | SW2: 12345678 | SW3: 12345678 |
|---|---|---|
| SD | 01000000 | 11000010 |
| OSPI | 00000000 | 11001110 |
| EMMC | 00000000 | 11010010 |
| UART | 00000000 | 11011100 |
| USB DFU | 00000000 | 11001010 |
For SW2 and SW1, the switch state in the "ON" position = 1.
See Common Debugging environment - OpenOCD<k3_rst_refer_openocd>: for detailed setup information.
Warning
OpenOCD support since: August 2023 (git master)
Until the next stable release of OpenOCD is available in your development environment's distribution, it might be necessary to build OpenOCD from the source.
To start OpenOCD and connect to the board
openocd -f board/ti_am62a7evm.cfg