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shader.cc
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shader.cc
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// Copyright (c) 2009-2011, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda,
// George L. Yuan, Andrew Turner, Inderpreet Singh
// The University of British Columbia
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution. Neither the name of
// The University of British Columbia nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
#include "shader.h"
#include <float.h>
#include <limits.h>
#include <string.h>
#include "../../libcuda/gpgpu_context.h"
#include "../cuda-sim/cuda-sim.h"
#include "../cuda-sim/ptx-stats.h"
#include "../cuda-sim/ptx_sim.h"
#include "../statwrapper.h"
#include "addrdec.h"
#include "dram.h"
#include "gpu-misc.h"
#include "gpu-sim.h"
#include "icnt_wrapper.h"
#include "mem_fetch.h"
#include "mem_latency_stat.h"
#include "shader_trace.h"
#include "stat-tool.h"
#include "traffic_breakdown.h"
#include "visualizer.h"
#define PRIORITIZE_MSHR_OVER_WB 1
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
mem_fetch *shader_core_mem_fetch_allocator::alloc(
new_addr_type addr, mem_access_type type, unsigned size, bool wr,
unsigned long long cycle) const {
mem_access_t access(type, addr, size, wr, m_memory_config->gpgpu_ctx);
mem_fetch *mf =
new mem_fetch(access, NULL, wr ? WRITE_PACKET_SIZE : READ_PACKET_SIZE, -1,
m_core_id, m_cluster_id, m_memory_config, cycle);
return mf;
}
/////////////////////////////////////////////////////////////////////////////
std::list<unsigned> shader_core_ctx::get_regs_written(const inst_t &fvt) const {
std::list<unsigned> result;
for (unsigned op = 0; op < MAX_REG_OPERANDS; op++) {
int reg_num = fvt.arch_reg.dst[op]; // this math needs to match that used
// in function_info::ptx_decode_inst
if (reg_num >= 0) // valid register
result.push_back(reg_num);
}
return result;
}
void exec_shader_core_ctx::create_shd_warp() {
m_warp.resize(m_config->max_warps_per_shader);
for (unsigned k = 0; k < m_config->max_warps_per_shader; ++k) {
m_warp[k] = new shd_warp_t(this, m_config->warp_size);
}
}
void shader_core_ctx::create_front_pipeline() {
// pipeline_stages is the sum of normal pipeline stages and specialized_unit
// stages * 2 (for ID and EX)
unsigned total_pipeline_stages =
N_PIPELINE_STAGES + m_config->m_specialized_unit.size() * 2;
m_pipeline_reg.reserve(total_pipeline_stages);
for (int j = 0; j < N_PIPELINE_STAGES; j++) {
m_pipeline_reg.push_back(
register_set(m_config->pipe_widths[j], pipeline_stage_name_decode[j]));
}
for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].id_oc_spec_reg_width,
m_config->m_specialized_unit[j].name));
m_config->m_specialized_unit[j].ID_OC_SPEC_ID = m_pipeline_reg.size() - 1;
m_specilized_dispatch_reg.push_back(
&m_pipeline_reg[m_pipeline_reg.size() - 1]);
}
for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].oc_ex_spec_reg_width,
m_config->m_specialized_unit[j].name));
m_config->m_specialized_unit[j].OC_EX_SPEC_ID = m_pipeline_reg.size() - 1;
}
if (m_config->sub_core_model) {
// in subcore model, each scheduler should has its own issue register, so
// num scheduler = reg width
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_SP].get_size());
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_SFU].get_size());
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_MEM].get_size());
if (m_config->gpgpu_tensor_core_avail)
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_TENSOR_CORE].get_size());
if (m_config->gpgpu_num_dp_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_DP].get_size());
if (m_config->gpgpu_num_int_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_INT].get_size());
if (m_config->gpgpu_num_rt_core_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_RT].get_size());
}
m_threadState = (thread_ctx_t *)calloc(sizeof(thread_ctx_t),
m_config->n_thread_per_shader);
m_not_completed = 0;
m_active_threads.reset();
m_n_active_cta = 0;
for (unsigned i = 0; i < MAX_CTA_PER_SHADER; i++) m_cta_status[i] = 0;
for (unsigned i = 0; i < m_config->n_thread_per_shader; i++) {
m_thread[i] = NULL;
m_threadState[i].m_cta_id = -1;
m_threadState[i].m_active = false;
}
// m_icnt = new shader_memory_interface(this,cluster);
if (m_config->gpgpu_perfect_mem) {
m_icnt = new perfect_memory_interface(this, m_cluster);
} else {
m_icnt = new shader_memory_interface(this, m_cluster);
}
m_mem_fetch_allocator =
new shader_core_mem_fetch_allocator(m_sid, m_tpc, m_memory_config);
// fetch
m_last_warp_fetched = 0;
#define STRSIZE 1024
char name[STRSIZE];
snprintf(name, STRSIZE, "L1I_%03d", m_sid);
m_L1I = new read_only_cache(name, m_config->m_L1I_config, m_sid,
get_shader_instruction_cache_id(), m_icnt,
IN_L1I_MISS_QUEUE);
}
void shader_core_ctx::create_schedulers() {
m_scoreboard = new Scoreboard(m_sid, m_config->max_warps_per_shader, m_gpu);
// scedulers
// must currently occur after all inputs have been initialized.
std::string sched_config = m_config->gpgpu_scheduler_string;
const concrete_scheduler scheduler =
sched_config.find("lrr") != std::string::npos
? CONCRETE_SCHEDULER_LRR
: sched_config.find("two_level_active") != std::string::npos
? CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE
: sched_config.find("gto") != std::string::npos
? CONCRETE_SCHEDULER_GTO
: sched_config.find("old") != std::string::npos
? CONCRETE_SCHEDULER_OLDEST_FIRST
: sched_config.find("warp_limiting") !=
std::string::npos
? CONCRETE_SCHEDULER_WARP_LIMITING
: NUM_CONCRETE_SCHEDULERS;
assert(scheduler != NUM_CONCRETE_SCHEDULERS);
for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) {
switch (scheduler) {
case CONCRETE_SCHEDULER_LRR:
schedulers.push_back(new lrr_scheduler(
m_stats, this, m_scoreboard, m_simt_stack, m_simt_tables, &m_warp,
&m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP],
&m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT],
&m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_RT], m_specilized_dispatch_reg,
&m_pipeline_reg[ID_OC_MEM], i));
break;
case CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE:
schedulers.push_back(new two_level_active_scheduler(
m_stats, this, m_scoreboard, m_simt_stack, m_simt_tables, &m_warp,
&m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP],
&m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT],
&m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_RT], m_specilized_dispatch_reg,
&m_pipeline_reg[ID_OC_MEM], i, m_config->gpgpu_scheduler_string));
break;
case CONCRETE_SCHEDULER_GTO:
schedulers.push_back(new gto_scheduler(
m_stats, this, m_scoreboard, m_simt_stack, m_simt_tables, &m_warp,
&m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP],
&m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT],
&m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_RT], m_specilized_dispatch_reg,
&m_pipeline_reg[ID_OC_MEM], i));
break;
case CONCRETE_SCHEDULER_OLDEST_FIRST:
schedulers.push_back(new oldest_scheduler(
m_stats, this, m_scoreboard, m_simt_stack, m_simt_tables, &m_warp,
&m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP],
&m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT],
&m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_RT], m_specilized_dispatch_reg,
&m_pipeline_reg[ID_OC_MEM], i));
break;
case CONCRETE_SCHEDULER_WARP_LIMITING:
schedulers.push_back(new swl_scheduler(
m_stats, this, m_scoreboard, m_simt_stack, m_simt_tables, &m_warp,
&m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP],
&m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT],
&m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_RT], m_specilized_dispatch_reg,
&m_pipeline_reg[ID_OC_MEM], i, m_config->gpgpu_scheduler_string));
break;
default:
abort();
};
}
for (unsigned i = 0; i < m_warp.size(); i++) {
// distribute i's evenly though schedulers;
schedulers[i % m_config->gpgpu_num_sched_per_core]->add_supervised_warp_id(
i);
}
for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; ++i) {
schedulers[i]->done_adding_supervised_warps();
}
}
void shader_core_ctx::create_exec_pipeline() {
// op collector configuration
enum { SP_CUS, DP_CUS, SFU_CUS, TENSOR_CORE_CUS, INT_CUS, MEM_CUS, GEN_CUS };
opndcoll_rfu_t::port_vector_t in_ports;
opndcoll_rfu_t::port_vector_t out_ports;
opndcoll_rfu_t::uint_vector_t cu_sets;
// configure generic collectors
m_operand_collector.add_cu_set(
GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen,
m_config->gpgpu_operand_collector_num_out_ports_gen);
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_gen;
i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
if (m_config->gpgpu_tensor_core_avail) {
in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]);
out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]);
}
if (m_config->gpgpu_num_dp_units > 0) {
in_ports.push_back(&m_pipeline_reg[ID_OC_DP]);
out_ports.push_back(&m_pipeline_reg[OC_EX_DP]);
}
if (m_config->gpgpu_num_int_units > 0) {
in_ports.push_back(&m_pipeline_reg[ID_OC_INT]);
out_ports.push_back(&m_pipeline_reg[OC_EX_INT]);
}
if (m_config->gpgpu_num_rt_core_units > 0) {
in_ports.push_back(&m_pipeline_reg[ID_OC_RT]);
out_ports.push_back(&m_pipeline_reg[OC_EX_RT]);
}
if (m_config->m_specialized_unit.size() > 0) {
for (unsigned j = 0; j < m_config->m_specialized_unit.size(); ++j) {
in_ports.push_back(
&m_pipeline_reg[m_config->m_specialized_unit[j].ID_OC_SPEC_ID]);
out_ports.push_back(
&m_pipeline_reg[m_config->m_specialized_unit[j].OC_EX_SPEC_ID]);
}
}
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports, out_ports, cu_sets);
in_ports.clear(), out_ports.clear(), cu_sets.clear();
}
if (m_config->enable_specialized_operand_collector) {
m_operand_collector.add_cu_set(
SP_CUS, m_config->gpgpu_operand_collector_num_units_sp,
m_config->gpgpu_operand_collector_num_out_ports_sp);
m_operand_collector.add_cu_set(
DP_CUS, m_config->gpgpu_operand_collector_num_units_dp,
m_config->gpgpu_operand_collector_num_out_ports_dp);
m_operand_collector.add_cu_set(
TENSOR_CORE_CUS,
m_config->gpgpu_operand_collector_num_units_tensor_core,
m_config->gpgpu_operand_collector_num_out_ports_tensor_core);
m_operand_collector.add_cu_set(
SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu,
m_config->gpgpu_operand_collector_num_out_ports_sfu);
m_operand_collector.add_cu_set(
MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem,
m_config->gpgpu_operand_collector_num_out_ports_mem);
m_operand_collector.add_cu_set(
INT_CUS, m_config->gpgpu_operand_collector_num_units_int,
m_config->gpgpu_operand_collector_num_out_ports_int);
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sp;
i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
cu_sets.push_back((unsigned)SP_CUS);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports, out_ports, cu_sets);
in_ports.clear(), out_ports.clear(), cu_sets.clear();
}
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_dp;
i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_DP]);
out_ports.push_back(&m_pipeline_reg[OC_EX_DP]);
cu_sets.push_back((unsigned)DP_CUS);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports, out_ports, cu_sets);
in_ports.clear(), out_ports.clear(), cu_sets.clear();
}
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sfu;
i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
cu_sets.push_back((unsigned)SFU_CUS);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports, out_ports, cu_sets);
in_ports.clear(), out_ports.clear(), cu_sets.clear();
}
for (unsigned i = 0;
i < m_config->gpgpu_operand_collector_num_in_ports_tensor_core; i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]);
out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]);
cu_sets.push_back((unsigned)TENSOR_CORE_CUS);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports, out_ports, cu_sets);
in_ports.clear(), out_ports.clear(), cu_sets.clear();
}
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_mem;
i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
cu_sets.push_back((unsigned)MEM_CUS);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports, out_ports, cu_sets);
in_ports.clear(), out_ports.clear(), cu_sets.clear();
}
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_int;
i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_INT]);
out_ports.push_back(&m_pipeline_reg[OC_EX_INT]);
cu_sets.push_back((unsigned)INT_CUS);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports, out_ports, cu_sets);
in_ports.clear(), out_ports.clear(), cu_sets.clear();
}
}
m_operand_collector.init(m_config->gpgpu_num_reg_banks, this);
m_num_function_units =
m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units +
m_config->gpgpu_num_sfu_units + m_config->gpgpu_num_tensor_core_units +
m_config->gpgpu_num_int_units + m_config->m_specialized_unit_num +
1 + 1; // sp_unit, sfu, dp, tensor, int, rt_unit, ldst_unit
// m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ];
// m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ];
// m_fu = new simd_function_unit*[m_num_function_units];
for (int k = 0; k < m_config->gpgpu_num_sp_units; k++) {
m_fu.push_back(new sp_unit(&m_pipeline_reg[EX_WB], m_config, this));
m_dispatch_port.push_back(ID_OC_SP);
m_issue_port.push_back(OC_EX_SP);
}
for (int k = 0; k < m_config->gpgpu_num_dp_units; k++) {
m_fu.push_back(new dp_unit(&m_pipeline_reg[EX_WB], m_config, this));
m_dispatch_port.push_back(ID_OC_DP);
m_issue_port.push_back(OC_EX_DP);
}
for (int k = 0; k < m_config->gpgpu_num_int_units; k++) {
m_fu.push_back(new int_unit(&m_pipeline_reg[EX_WB], m_config, this));
m_dispatch_port.push_back(ID_OC_INT);
m_issue_port.push_back(OC_EX_INT);
}
for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) {
m_fu.push_back(new sfu(&m_pipeline_reg[EX_WB], m_config, this));
m_dispatch_port.push_back(ID_OC_SFU);
m_issue_port.push_back(OC_EX_SFU);
}
for (int k = 0; k < m_config->gpgpu_num_tensor_core_units; k++) {
m_fu.push_back(new tensor_core(&m_pipeline_reg[EX_WB], m_config, this));
m_dispatch_port.push_back(ID_OC_TENSOR_CORE);
m_issue_port.push_back(OC_EX_TENSOR_CORE);
}
for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
for (unsigned k = 0; k < m_config->m_specialized_unit[j].num_units; k++) {
m_fu.push_back(new specialized_unit(
&m_pipeline_reg[EX_WB], m_config, this, SPEC_UNIT_START_ID + j,
m_config->m_specialized_unit[j].name,
m_config->m_specialized_unit[j].latency));
m_dispatch_port.push_back(m_config->m_specialized_unit[j].ID_OC_SPEC_ID);
m_issue_port.push_back(m_config->m_specialized_unit[j].OC_EX_SPEC_ID);
}
}
m_ldst_unit = new ldst_unit(m_icnt, m_mem_fetch_allocator, this,
&m_operand_collector, m_scoreboard, m_config,
m_memory_config, m_stats, m_sid, m_tpc);
m_fu.push_back(m_ldst_unit);
m_dispatch_port.push_back(ID_OC_MEM);
m_issue_port.push_back(OC_EX_MEM);
m_rt_unit = new rt_unit(m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, m_config, m_stats, m_sid, m_tpc);
m_fu.push_back(m_rt_unit);
m_dispatch_port.push_back(ID_OC_RT);
m_issue_port.push_back(OC_EX_RT);
assert(m_num_function_units == m_fu.size() and
m_fu.size() == m_dispatch_port.size() and
m_fu.size() == m_issue_port.size());
// there are as many result buses as the width of the EX_WB stage
num_result_bus = m_config->pipe_widths[EX_WB];
for (unsigned i = 0; i < num_result_bus; i++) {
this->m_result_bus.push_back(new std::bitset<MAX_ALU_LATENCY>());
}
if (m_config->model == AWARE_RECONVERGENCE)
updateSIMTDivergenceStructuresInitialization();
}
shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu,
class simt_core_cluster *cluster,
unsigned shader_id, unsigned tpc_id,
const shader_core_config *config,
const memory_config *mem_config,
shader_core_stats *stats)
: core_t(gpu, NULL, config->warp_size, config->n_thread_per_shader),
m_barriers(this, config->max_warps_per_shader, config->max_cta_per_core,
config->max_barriers_per_cta, config->warp_size),
m_active_warps(0),
m_dynamic_warp_id(0) {
m_cluster = cluster;
m_config = config;
m_memory_config = mem_config;
m_stats = stats;
unsigned warp_size = config->warp_size;
Issue_Prio = 0;
m_sid = shader_id;
m_tpc = tpc_id;
m_last_inst_gpu_sim_cycle = 0;
m_last_inst_gpu_tot_sim_cycle = 0;
// Jin: for concurrent kernels on a SM
m_occupied_n_threads = 0;
m_occupied_shmem = 0;
m_occupied_regs = 0;
m_occupied_ctas = 0;
m_occupied_hwtid.reset();
m_occupied_cta_to_hwtid.clear();
}
void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread,
bool reset_not_completed) {
if (reset_not_completed) {
m_not_completed = 0;
m_active_threads.reset();
// Jin: for concurrent kernels on a SM
m_occupied_n_threads = 0;
m_occupied_shmem = 0;
m_occupied_regs = 0;
m_occupied_ctas = 0;
m_occupied_hwtid.reset();
m_occupied_cta_to_hwtid.clear();
m_active_warps = 0;
}
for (unsigned i = start_thread; i < end_thread; i++) {
m_threadState[i].n_insn = 0;
m_threadState[i].m_cta_id = -1;
}
for (unsigned i = start_thread / m_config->warp_size;
i < end_thread / m_config->warp_size; ++i) {
m_warp[i]->reset();
if (m_config->model == 1) {
m_simt_stack[i]->reset();
} else {
m_simt_tables[i]->reset();
}
}
}
void shader_core_ctx::init_warps(unsigned cta_id, unsigned start_thread,
unsigned end_thread, unsigned ctaid,
int cta_size, kernel_info_t &kernel) {
//
address_type start_pc = next_pc(start_thread);
unsigned kernel_id = kernel.get_uid();
unsigned start_warp = start_thread / m_config->warp_size;
unsigned warp_per_cta = cta_size / m_config->warp_size;
unsigned end_warp = end_thread / m_config->warp_size +
((end_thread % m_config->warp_size) ? 1 : 0);
for (unsigned i = start_warp; i < end_warp; ++i) {
unsigned n_active = 0;
simt_mask_t active_threads;
for (unsigned t = 0; t < m_config->warp_size; t++) {
unsigned hwtid = i * m_config->warp_size + t;
if (hwtid < end_thread) {
n_active++;
assert(!m_active_threads.test(hwtid));
m_active_threads.set(hwtid);
active_threads.set(t);
}
}
if (m_config->model == POST_DOMINATOR) {
m_simt_stack[i]->launch(start_pc, active_threads);
if (m_gpu->resume_option == 1 && kernel_id == m_gpu->resume_kernel &&
ctaid >= m_gpu->resume_CTA && ctaid < m_gpu->checkpoint_CTA_t) {
char fname[2048];
snprintf(fname, 2048, "checkpoint_files/warp_%d_%d_simt.txt",
i % warp_per_cta, ctaid);
unsigned pc, rpc;
m_simt_stack[i]->resume(fname);
m_simt_stack[i]->get_pdom_stack_top_info(&pc, &rpc);
for (unsigned t = 0; t < m_config->warp_size; t++) {
if (m_thread != NULL) {
m_thread[i * m_config->warp_size + t]->set_npc(pc);
m_thread[i * m_config->warp_size + t]->update_pc();
}
}
start_pc = pc;
}
} else {
m_simt_tables[i]->launch(start_pc, active_threads);
}
m_warp[i]->init(start_pc, cta_id, i, active_threads, m_dynamic_warp_id);
++m_dynamic_warp_id;
m_not_completed += n_active;
++m_active_warps;
}
}
// return the next pc of a thread
address_type shader_core_ctx::next_pc(int tid) const {
if (tid == -1) return -1;
ptx_thread_info *the_thread = m_thread[tid];
if (the_thread == NULL) return -1;
return the_thread
->get_pc(); // PC should already be updatd to next PC at this point (was
// set in shader_decode() last time thread ran)
}
void gpgpu_sim::get_pdom_stack_top_info(unsigned sid, unsigned tid,
unsigned *pc, unsigned *rpc) {
unsigned cluster_id = m_shader_config->sid_to_cluster(sid);
m_cluster[cluster_id]->get_pdom_stack_top_info(sid, tid, pc, rpc);
}
void shader_core_ctx::get_pdom_stack_top_info(unsigned tid, unsigned *pc,
unsigned *rpc) const {
unsigned warp_id = tid / m_config->warp_size;
if (m_config->model == 1){
m_simt_stack[warp_id]->get_pdom_stack_top_info(pc, rpc);
} else {
m_simt_tables[warp_id]->get_pdom_active_split_info(pc, rpc);
}
}
float shader_core_ctx::get_current_occupancy(unsigned long long &active,
unsigned long long &total) const {
// To match the achieved_occupancy in nvprof, only SMs that are active are
// counted toward the occupancy.
if (m_active_warps > 0) {
total += m_warp.size();
active += m_active_warps;
return float(active) / float(total);
} else {
return 0;
}
}
void shader_core_stats::print_roofline(FILE *fout) const {
std::vector<float> op_int, perf;
std::string op_int_str, perf_str, cacheline_str, int_str, cycle_str;
float op_int_sum = 0, perf_sum = 0;
for (unsigned i=0; i<m_config->num_shader(); i++) {
float o = (float)rt_total_intersection_stages[i] / (float)rt_total_cacheline_fetched[i];
float p = (float)rt_total_intersection_stages[i] / (float)rt_total_cycles[i];
assert(rt_total_cacheline_fetched[i] <= rt_total_cycles[i]);
op_int.push_back(o);
perf.push_back(p);
op_int_sum += o;
perf_sum += p;
op_int_str.append(std::to_string(o));
op_int_str.append("\t");
perf_str.append(std::to_string(p));
perf_str.append("\t");
cacheline_str.append(std::to_string(rt_total_cacheline_fetched[i]));
cacheline_str.append("\t");
int_str.append(std::to_string(rt_total_intersection_stages[i]));
int_str.append("\t");
}
fprintf(fout, "rt_total_cacheline_fetched = %s\n", cacheline_str.c_str());
fprintf(fout, "rt_total_intersection_stages = %s\n", int_str.c_str());
fprintf(fout, "rt_op_intensity = %s\n", op_int_str.c_str());
fprintf(fout, "rt_perf = %s\n", perf_str.c_str());
fprintf(fout, "rt_avg_op_intensity = %f\n", op_int_sum / m_config->num_shader());
fprintf(fout, "rt_avg_performance = %f\n", perf_sum / m_config->num_shader());
}
void shader_core_stats::print(FILE *fout) const {
unsigned long long thread_icount_uarch = 0;
unsigned long long warp_icount_uarch = 0;
for (unsigned i = 0; i < m_config->num_shader(); i++) {
thread_icount_uarch += m_num_sim_insn[i];
warp_icount_uarch += m_num_sim_winsn[i];
}
fprintf(fout, "gpgpu_n_tot_thrd_icount = %lld\n", thread_icount_uarch);
fprintf(fout, "gpgpu_n_tot_w_icount = %lld\n", warp_icount_uarch);
fprintf(fout, "gpgpu_n_stall_shd_mem = %d\n", gpgpu_n_stall_shd_mem);
fprintf(fout, "gpgpu_n_mem_read_local = %d\n", gpgpu_n_mem_read_local);
fprintf(fout, "gpgpu_n_mem_write_local = %d\n", gpgpu_n_mem_write_local);
fprintf(fout, "gpgpu_n_mem_read_global = %d\n", gpgpu_n_mem_read_global);
fprintf(fout, "gpgpu_n_mem_write_global = %d\n", gpgpu_n_mem_write_global);
fprintf(fout, "gpgpu_n_mem_texture = %d\n", gpgpu_n_mem_texture);
fprintf(fout, "gpgpu_n_mem_const = %d\n", gpgpu_n_mem_const);
fprintf(fout, "gpgpu_n_rt_mem:\n");
for (unsigned i=0; i<static_cast<int>(TransactionType::UNDEFINED); i++) {
fprintf(fout, "%d\t", gpgpu_n_rt_mem[i]);
}
fprintf(fout, "\n");
fprintf(fout, "gpgpu_n_local_load_insn = %d\n", gpgpu_n_local_load_insn);
fprintf(fout, "gpgpu_n_local_store_insn = %d\n", gpgpu_n_local_store_insn);
fprintf(fout, "gpgpu_n_global_load_insn = %d\n", gpgpu_n_global_load_insn);
fprintf(fout, "gpgpu_n_global_store_insn = %d\n", gpgpu_n_global_store_insn);
fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_shmem_insn);
fprintf(fout, "gpgpu_n_sstarr_insn = %d\n", gpgpu_n_sstarr_insn);
fprintf(fout, "gpgpu_n_tex_insn = %d\n", gpgpu_n_tex_insn);
fprintf(fout, "gpgpu_n_const_mem_insn = %d\n", gpgpu_n_const_insn);
fprintf(fout, "gpgpu_n_param_mem_insn = %d\n", gpgpu_n_param_insn);
fprintf(fout, "gpgpu_n_rt_insn = %d\n", gpgpu_n_rt_insn);
fprintf(fout, "gpgpu_n_rt_access_insn = %d\n", gpgpu_n_rt_access_insn);
fprintf(fout, "gpgpu_n_shmem_bkconflict = %d\n", gpgpu_n_shmem_bkconflict);
fprintf(fout, "gpgpu_n_cache_bkconflict = %d\n", gpgpu_n_cache_bkconflict);
fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n",
gpgpu_n_intrawarp_mshr_merge);
fprintf(fout, "gpgpu_n_cmem_portconflict = %d\n", gpgpu_n_cmem_portconflict);
fprintf(fout, "gpgpu_stall_shd_mem[c_mem][resource_stall] = %d\n",
gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]);
// fprintf(fout, "gpgpu_stall_shd_mem[c_mem][mshr_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[C_MEM][MSHR_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[c_mem][icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[C_MEM][ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[c_mem][data_port_stall] = %d\n",
// gpu_stall_shd_mem_breakdown[C_MEM][DATA_PORT_STALL]); fprintf(fout,
// "gpgpu_stall_shd_mem[t_mem][mshr_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[T_MEM][MSHR_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[t_mem][icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[T_MEM][ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[t_mem][data_port_stall] = %d\n",
// gpu_stall_shd_mem_breakdown[T_MEM][DATA_PORT_STALL]);
fprintf(fout, "gpgpu_stall_shd_mem[s_mem][bk_conf] = %d\n",
gpu_stall_shd_mem_breakdown[S_MEM][BK_CONF]);
fprintf(
fout, "gpgpu_stall_shd_mem[gl_mem][resource_stall] = %d\n",
gpu_stall_shd_mem_breakdown[G_MEM_LD][BK_CONF] +
gpu_stall_shd_mem_breakdown[G_MEM_ST][BK_CONF] +
gpu_stall_shd_mem_breakdown[L_MEM_LD][BK_CONF] +
gpu_stall_shd_mem_breakdown[L_MEM_ST][BK_CONF]); // coalescing stall
// at data cache
fprintf(
fout, "gpgpu_stall_shd_mem[gl_mem][coal_stall] = %d\n",
gpu_stall_shd_mem_breakdown[G_MEM_LD][COAL_STALL] +
gpu_stall_shd_mem_breakdown[G_MEM_ST][COAL_STALL] +
gpu_stall_shd_mem_breakdown[L_MEM_LD][COAL_STALL] +
gpu_stall_shd_mem_breakdown[L_MEM_ST][COAL_STALL]); // coalescing stall + bank
// conflict at data cache
fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][data_port_stall] = %d\n",
gpu_stall_shd_mem_breakdown[G_MEM_LD][DATA_PORT_STALL] +
gpu_stall_shd_mem_breakdown[G_MEM_ST][DATA_PORT_STALL] +
gpu_stall_shd_mem_breakdown[L_MEM_LD][DATA_PORT_STALL] +
gpu_stall_shd_mem_breakdown[L_MEM_ST][DATA_PORT_STALL]); // data port stall
// at data cache
// fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[G_MEM_LD][MSHR_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[G_MEM_LD][ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = %d\n",
// gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_CACHE_RSRV_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[G_MEM_ST][MSHR_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[G_MEM_ST][ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = %d\n",
// gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_CACHE_RSRV_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[L_MEM_LD][MSHR_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[L_MEM_LD][ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n",
// gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_CACHE_RSRV_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[L_MEM_ST][MSHR_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[L_MEM_ST][ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n",
// gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_ICNT_RC_FAIL]); fprintf(fout,
// "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n",
// gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_CACHE_RSRV_FAIL]);
fprintf(fout, "gpu_reg_bank_conflict_stalls = %d\n",
gpu_reg_bank_conflict_stalls);
unsigned long long gpgpusim_total_cycles = GPGPU_Context()->the_gpgpusim->g_the_gpu->gpu_sim_cycle + GPGPU_Context()->the_gpgpusim->g_the_gpu->gpu_tot_sim_cycle;
float average_rt_total_cycles = 0;
float average_mem_store_cycles = 0;
for (unsigned i=0; i<m_config->num_shader(); i++) {
average_rt_total_cycles += rt_total_cycles[i];
average_mem_store_cycles += rt_mem_store_q_cycles[i];
}
average_rt_total_cycles = average_rt_total_cycles / m_config->num_shader();
average_mem_store_cycles = average_mem_store_cycles / m_config->num_shader();
// RT unit stats
fprintf(fout, "rt_avg_warp_latency = %f\n", (float)rt_total_warp_latency / rt_total_warps);
fprintf(fout, "rt_avg_thread_latency = %f\n", (float)rt_total_thread_latency / rt_total_warps);
fprintf(fout, "rt_avg_efficiency = %f\n", (float)rt_total_simt_efficiency / rt_total_warps);
fprintf(fout, "rt_avg_warp_occupancy = %f\n", (float)rt_total_warp_latency / rt_total_cycles_sum / m_config->m_rt_max_warps);
print_roofline(fout);
fprintf(fout, "rt_writes = %d\n", rt_writes);
fprintf(fout, "rt_max_mem_store_q = %d\n", rt_max_store_q);
fprintf(fout, "rt_avg_mem_store_cycles = %f\n", average_mem_store_cycles);
fprintf(fout, "rt_cycles = %f\n", (float)average_rt_total_cycles / gpgpusim_total_cycles);
fprintf(fout, "rt_total_cycles = %f\n", average_rt_total_cycles);
fprintf(fout, "rt_total_cycles_sum = %d\n", rt_total_cycles_sum);
fprintf(fout, "rt_cycles_dist:");
for (unsigned i=0; i<m_config->num_shader(); i++) {
fprintf(fout, "\t%d", rt_total_cycles[i]);
}
fprintf(fout, "\n");
fprintf(fout, "rt_store_cycles_dist:");
for (unsigned i=0; i<m_config->num_shader(); i++) {
fprintf(fout, "\t%d", rt_mem_store_q_cycles[i]);
}
fprintf(fout, "\n");
fprintf(fout, "rt_latency_dist = ");
for (unsigned i=0; i<warp_statuses; i++) {
for (unsigned j=0; j<ray_statuses; j++) {
fprintf(fout, "%.2f\t", (float)rt_latency_dist[i][j] / rt_latency_counter);
}
}
fprintf(fout, "\n");
fprintf(fout, "warp_dist_rt = ");
for (unsigned i=0; i<11; i++) {
fprintf(fout, "%d\t", rt_warp_dist[i]);
}
fprintf(fout, "\n");
fprintf(fout, "warp_dist_empty = ");
for (unsigned i=0; i<11; i++) {
fprintf(fout, "%d\t", empty_warp_dist[i]);
}
fprintf(fout, "\n");
if (m_config->m_rt_coherence_engine) {
for (unsigned i=0; i<m_config->num_shader(); i++) {
fprintf(fout, "===========rt_coherence_engine[%d]===========\n", i);
rt_coherence_stats[i]->print(fout);
}
fprintf(fout, "---------------------------------------------\n");
}
fprintf(fout, "Warp Occupancy Distribution:\n");
fprintf(fout, "Stall:%d\t", shader_cycle_distro[2]);
fprintf(fout, "W0_Idle:%d\t", shader_cycle_distro[0]);
fprintf(fout, "W0_Scoreboard:%d", shader_cycle_distro[1]);
for (unsigned i = 3; i < m_config->warp_size + 3; i++)
fprintf(fout, "\tW%d:%d", i - 2, shader_cycle_distro[i]);
fprintf(fout, "\n");
fprintf(fout, "single_issue_nums: ");
for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++)
fprintf(fout, "WS%d:%d\t", i, single_issue_nums[i]);
fprintf(fout, "\n");
fprintf(fout, "dual_issue_nums: ");
for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++)
fprintf(fout, "WS%d:%d\t", i, dual_issue_nums[i]);
fprintf(fout, "\n");
m_outgoing_traffic_stats->print(fout);
m_incoming_traffic_stats->print(fout);
}
void shader_core_stats::event_warp_issued(unsigned s_id, unsigned warp_id,
unsigned num_issued,
unsigned dynamic_warp_id) {
assert(warp_id <= m_config->max_warps_per_shader);
for (unsigned i = 0; i < num_issued; ++i) {
if (m_shader_dynamic_warp_issue_distro[s_id].size() <= dynamic_warp_id) {
m_shader_dynamic_warp_issue_distro[s_id].resize(dynamic_warp_id + 1);
}
++m_shader_dynamic_warp_issue_distro[s_id][dynamic_warp_id];
if (m_shader_warp_slot_issue_distro[s_id].size() <= warp_id) {
m_shader_warp_slot_issue_distro[s_id].resize(warp_id + 1);
}
++m_shader_warp_slot_issue_distro[s_id][warp_id];
}
}
double shader_core_stats::compue_distribution_avg(std::map<unsigned/*sid*/, std::map<unsigned/*wid*/, std::map<unsigned/*# of entries*/, long long unsigned/*cycles*/>>> & dist) {
unsigned long long tot_cycles = 1;
unsigned long long tot_cycles_times_entries = 0;
for (auto it1=dist.begin(), et1=dist.end(); it1!=et1; it1++) {
unsigned sid = it1->first;
std::map<unsigned,std::map<unsigned,long long unsigned>> size_disto_within_core = dist[sid];
printf("sid=%u", sid);
for (auto it2=size_disto_within_core.begin(), et2=size_disto_within_core.end(); it2!=et2; it2++) {
unsigned wid = it2->first;
std::map<unsigned,long long unsigned> size_distro_within_warp = size_disto_within_core[wid];
printf(" wid=%u", wid);
for (auto it3=size_distro_within_warp.begin(), et3=size_distro_within_warp.end(); it3!=et3; it3++) {
unsigned numEntries = it3->first;
unsigned long long duration = it3->second;
tot_cycles_times_entries += (numEntries * duration);
tot_cycles += duration;
printf(" %u %llu\n", numEntries, duration);
}
}
}
dist.clear();
return ((double)tot_cycles_times_entries/(double)tot_cycles);
}
void shader_core_stats::print_reuse_distribution_avg() {
printf("Reuse Stats:\n");
std::map<unsigned, double> distToReuseMap;
std::map<unsigned, unsigned> distToReuseUpdatesMap;
distToReuseMap.clear();
for (auto it1=st_reuse_distro.begin(), et1=st_reuse_distro.end(); it1!=et1; it1++) {
unsigned sid = it1->first;
printf("sid=%u", sid);
std::map<unsigned,std::map<unsigned,long long unsigned>> st_reuse_disto_within_core = st_reuse_distro[sid];
for (auto it2=st_reuse_disto_within_core.begin(), et2=st_reuse_disto_within_core.end(); it2!=et2; it2++) {
unsigned wid = it2->first;
std::map<unsigned,long long unsigned> st_reuse_distro_within_warp = st_reuse_disto_within_core[wid];
printf(" wid=%u", wid);
for (auto it3=st_reuse_distro_within_warp.begin(), et3=st_reuse_distro_within_warp.end(); it3!=et3; it3++) {
unsigned dist = it3->first;
double reuse_duration = (double)it3->second;
assert(dist <= MAX_ST_SIZE);
unsigned updates = st_reuse_updates_distro[sid][wid][dist];
printf(" %u %f\n", dist, ((float)reuse_duration/updates));
if (distToReuseMap.find(dist) == distToReuseMap.end()) {
distToReuseMap[dist] = 0;
}
if (dist > 0) {
distToReuseMap[dist] += reuse_duration;
}
distToReuseUpdatesMap[dist] += updates;
}
}
}
printf("Overall Average:\n");
for (auto it=distToReuseMap.begin(), et=distToReuseMap.end(); it!=et; it++) {
unsigned dist = it->first;
double reuse_duration = it->second;
unsigned updates = distToReuseUpdatesMap[dist];
printf("dist=%u %f\n", dist, (reuse_duration/updates));
}
}
void shader_core_stats::visualizer_print(gzFile visualizer_file) {
// warp divergence breakdown
gzprintf(visualizer_file, "WarpDivergenceBreakdown:");
unsigned int total = 0;
unsigned int cf =
(m_config->gpgpu_warpdistro_shader == -1) ? m_config->num_shader() : 1;
gzprintf(visualizer_file, " %d",
(shader_cycle_distro[0] - last_shader_cycle_distro[0]) / cf);
gzprintf(visualizer_file, " %d",
(shader_cycle_distro[1] - last_shader_cycle_distro[1]) / cf);
gzprintf(visualizer_file, " %d",
(shader_cycle_distro[2] - last_shader_cycle_distro[2]) / cf);
for (unsigned i = 0; i < m_config->warp_size + 3; i++) {
if (i >= 3) {
total += (shader_cycle_distro[i] - last_shader_cycle_distro[i]);
if (((i - 3) % (m_config->warp_size / 8)) ==
((m_config->warp_size / 8) - 1)) {
gzprintf(visualizer_file, " %d", total / cf);
total = 0;
}
}
last_shader_cycle_distro[i] = shader_cycle_distro[i];
}
gzprintf(visualizer_file, "\n");
gzprintf(visualizer_file, "RTWarpDist:");
gzprintf(visualizer_file, " %d", n_empty_warps);
gzprintf(visualizer_file, " %d", n_shd_warps);
gzprintf(visualizer_file, " %d", n_rt_warps);
gzprintf(visualizer_file, "\n");
gzprintf(visualizer_file, "ctas_completed: %d\n", ctas_completed);
ctas_completed = 0;
// warp issue breakdown
unsigned sid = m_config->gpgpu_warp_issue_shader;
unsigned count = 0;
unsigned warp_id_issued_sum = 0;
gzprintf(visualizer_file, "WarpIssueSlotBreakdown:");
if (m_shader_warp_slot_issue_distro[sid].size() > 0) {
for (std::vector<unsigned>::const_iterator iter =
m_shader_warp_slot_issue_distro[sid].begin();
iter != m_shader_warp_slot_issue_distro[sid].end(); iter++, count++) {
unsigned diff = count < m_last_shader_warp_slot_issue_distro.size()
? *iter - m_last_shader_warp_slot_issue_distro[count]
: *iter;
gzprintf(visualizer_file, " %d", diff);
warp_id_issued_sum += diff;
}
m_last_shader_warp_slot_issue_distro = m_shader_warp_slot_issue_distro[sid];
} else {
gzprintf(visualizer_file, " 0");
}
gzprintf(visualizer_file, "\n");
#define DYNAMIC_WARP_PRINT_RESOLUTION 32
unsigned total_issued_this_resolution = 0;
unsigned dynamic_id_issued_sum = 0;
count = 0;
gzprintf(visualizer_file, "WarpIssueDynamicIdBreakdown:");
if (m_shader_dynamic_warp_issue_distro[sid].size() > 0) {
for (std::vector<unsigned>::const_iterator iter =
m_shader_dynamic_warp_issue_distro[sid].begin();
iter != m_shader_dynamic_warp_issue_distro[sid].end();
iter++, count++) {
unsigned diff =
count < m_last_shader_dynamic_warp_issue_distro.size()
? *iter - m_last_shader_dynamic_warp_issue_distro[count]
: *iter;
total_issued_this_resolution += diff;
if ((count + 1) % DYNAMIC_WARP_PRINT_RESOLUTION == 0) {
gzprintf(visualizer_file, " %d", total_issued_this_resolution);
dynamic_id_issued_sum += total_issued_this_resolution;
total_issued_this_resolution = 0;
}
}
if (count % DYNAMIC_WARP_PRINT_RESOLUTION != 0) {
gzprintf(visualizer_file, " %d", total_issued_this_resolution);
dynamic_id_issued_sum += total_issued_this_resolution;
}
m_last_shader_dynamic_warp_issue_distro =
m_shader_dynamic_warp_issue_distro[sid];