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LPfilter.xco
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LPfilter.xco
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##############################################################
#
# Xilinx Core Generator version 11.1
# Date: Mon Mar 22 07:51:20 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s1200e
SET devicefamily = spartan3e
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 4.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET chan_in_adv=0
CSET clock_frequency=50.0
CSET coefficient_buffer_type=Automatic
CSET coefficient_file="C:\Documents and Settings\Umut Gultepe.PC245486007190\My Documents\MATLAB\coef.coe"
CSET coefficient_fractional_bits=0
CSET coefficient_reload=false
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Inferred
CSET coefficient_width=16
CSET column_wrap_length=16
CSET component_name=LPfilter
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Unsigned
CSET data_width=12
CSET decimation_rate=1
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Single_Rate
CSET first_column_length=16
CSET has_ce=false
CSET has_data_valid=false
CSET has_nd=false
CSET has_sclr=false
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=1
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=1
CSET optimization_goal=Area
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Truncate_LSBs
CSET output_width=12
CSET passband_max=0.5
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET rate_change_type=Integer
CSET registered_output=true
CSET sample_frequency=0.250
CSET sclr_deterministic=false
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
GENERATE
# CRC: 96bad8ae