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iocanxx.h
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iocanxx.h
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/* Copyright (c) 2004,2005,2006 Colin O'Flynn <coflynn@newae.com>
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
/* $Id$ */
/* This file is based largely on:
- iom128.h by Peter Jansen (bit defines)
- iom169.h by Juergen Schilling <juergen.schilling@honeywell.com>
(register addresses)
- AT90CAN128 Datasheet (bit defines and register addresses)
- Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need
to change) */
/* iocanxx.h - definitions for AT90CAN32, AT90CAN64 and AT90CAN128 */
#ifndef _AVR_IOCANXX_H_
#define _AVR_IOCANXX_H_ 1
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iocanxx.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
/* I/O registers and bit definitions. */
/* RegDef: Port A */
#define PINA _SFR_IO8(0x00)
#define DDRA _SFR_IO8(0x01)
#define PORTA _SFR_IO8(0x02)
/* RegDef: Port B */
#define PINB _SFR_IO8(0x03)
#define DDRB _SFR_IO8(0x04)
#define PORTB _SFR_IO8(0x05)
/* RegDef: Port C */
#define PINC _SFR_IO8(0x06)
#define DDRC _SFR_IO8(0x07)
#define PORTC _SFR_IO8(0x08)
/* RegDef: Port D */
#define PIND _SFR_IO8(0x09)
#define DDRD _SFR_IO8(0x0A)
#define PORTD _SFR_IO8(0x0B)
/* RegDef: Port E */
#define PINE _SFR_IO8(0x0C)
#define DDRE _SFR_IO8(0x0D)
#define PORTE _SFR_IO8(0x0E)
/* RegDef: Port F */
#define PINF _SFR_IO8(0x0F)
#define DDRF _SFR_IO8(0x10)
#define PORTF _SFR_IO8(0x11)
/* RegDef: Port G */
#define PING _SFR_IO8(0x12)
#define DDRG _SFR_IO8(0x13)
#define PORTG _SFR_IO8(0x14)
/* RegDef: Timer/Counter 0 interrupt Flag Register */
#define TIFR0 _SFR_IO8(0x15)
/* RegDef: Timer/Counter 1 interrupt Flag Register */
#define TIFR1 _SFR_IO8(0x16)
/* RegDef: Timer/Counter 2 interrupt Flag Register */
#define TIFR2 _SFR_IO8(0x17)
/* RegDef: Timer/Counter 3 interrupt Flag Register */
#define TIFR3 _SFR_IO8(0x18)
/* RegDef: External Interrupt Flag Register */
#define EIFR _SFR_IO8(0x1C)
/* RegDef: External Interrupt Mask Register */
#define EIMSK _SFR_IO8(0x1D)
/* RegDef: General Purpose I/O Register 0 */
#define GPIOR0 _SFR_IO8(0x1E)
/* RegDef: EEPROM Control Register */
#define EECR _SFR_IO8(0x1F)
/* RegDef: EEPROM Data Register */
#define EEDR _SFR_IO8(0x20)
/* RegDef: EEPROM Address Register */
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0x22)
/* 6-char sequence denoting where to find the EEPROM registers in memory space.
Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
subroutines.
First two letters: EECR address.
Second two letters: EEDR address.
Last two letters: EEAR address. */
#define __EEPROM_REG_LOCATIONS__ 1F2021
/* RegDef: General Timer/Counter Control Register */
#define GTCCR _SFR_IO8(0x23)
/* RegDef: Timer/Counter Control Register A */
#define TCCR0A _SFR_IO8(0x24)
/* RegDef: Timer/Counter Register */
#define TCNT0 _SFR_IO8(0x26)
/* RegDef: Output Compare Register A */
#define OCR0A _SFR_IO8(0x27)
/* RegDef: General Purpose I/O Register 1 */
#define GPIOR1 _SFR_IO8(0x2A)
/* RegDef: General Purpose I/O Register 2 */
#define GPIOR2 _SFR_IO8(0x2B)
/* RegDef: SPI Control Register */
#define SPCR _SFR_IO8(0x2C)
/* RegDef: SPI Status Register */
#define SPSR _SFR_IO8(0x2D)
/* RegDef: SPI Data Register */
#define SPDR _SFR_IO8(0x2E)
/* RegDef: Analog Comperator Control and Status Register */
#define ACSR _SFR_IO8(0x30)
/* RegDef: On-chip Debug Register */
#define OCDR _SFR_IO8(0x31)
/* RegDef: Sleep Mode Control Register */
#define SMCR _SFR_IO8(0x33)
/* RegDef: MCU Status Register */
#define MCUSR _SFR_IO8(0x34)
/* RegDef: MCU Control Rgeister */
#define MCUCR _SFR_IO8(0x35)
/* RegDef: Store Program Memory Control and Status Register */
#define SPMCSR _SFR_IO8(0x37)
/* RegDef: RAMPZ register. */
#define RAMPZ _SFR_IO8(0x3B)
/* RegDef: Watchdog Timer Control Register */
#define WDTCR _SFR_MEM8(0x60)
/* RegDef: Clock Prescale Register */
#define CLKPR _SFR_MEM8(0x61)
/* RegDef: Oscillator Calibration Register */
#define OSCCAL _SFR_MEM8(0x66)
/* RegDef: External Interrupt Control Register A */
#define EICRA _SFR_MEM8(0x69)
/* RegDef: External Interrupt Control Register B */
#define EICRB _SFR_MEM8(0x6A)
/* RegDef: Timer/Counter 0 Interrupt Mask Register */
#define TIMSK0 _SFR_MEM8(0x6E)
/* RegDef: Timer/Counter 1 Interrupt Mask Register */
#define TIMSK1 _SFR_MEM8(0x6F)
/* RegDef: Timer/Counter 2 Interrupt Mask Register */
#define TIMSK2 _SFR_MEM8(0x70)
/* RegDef: Timer/Counter 3 Interrupt Mask Register */
#define TIMSK3 _SFR_MEM8(0x71)
/* RegDef: External Memory Control Register A */
#define XMCRA _SFR_MEM8(0x74)
/* RegDef: External Memory Control Register A */
#define XMCRB _SFR_MEM8(0x75)
/* RegDef: ADC Data Register */
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCH _SFR_MEM8(0x79)
/* RegDef: ADC Control and Status Register A */
#define ADCSRA _SFR_MEM8(0x7A)
/* RegDef: ADC Control and Status Register B */
#define ADCSRB _SFR_MEM8(0x7B)
/* RegDef: ADC Multiplex Selection Register */
#define ADMUX _SFR_MEM8(0x7C)
/* RegDef: Digital Input Disable Register 0 */
#define DIDR0 _SFR_MEM8(0x7E)
/* RegDef: Digital Input Disable Register 1 */
#define DIDR1 _SFR_MEM8(0x7F)
/* RegDef: Timer/Counter1 Control Register A */
#define TCCR1A _SFR_MEM8(0x80)
/* RegDef: Timer/Counter1 Control Register B */
#define TCCR1B _SFR_MEM8(0x81)
/* RegDef: Timer/Counter1 Control Register C */
#define TCCR1C _SFR_MEM8(0x82)
/* RegDef: Timer/Counter1 Register */
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1H _SFR_MEM8(0x85)
/* RegDef: Timer/Counter1 Input Capture Register */
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1H _SFR_MEM8(0x87)
/* RegDef: Timer/Counter1 Output Compare Register A */
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AH _SFR_MEM8(0x89)
/* RegDef: Timer/Counter1 Output Compare Register B */
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BH _SFR_MEM8(0x8B)
/* RegDef: Timer/Counter1 Output Compare Register C */
#define OCR1C _SFR_MEM16(0x8C)
#define OCR1CL _SFR_MEM8(0x8C)
#define OCR1CH _SFR_MEM8(0x8D)
/* RegDef: Timer/Counter3 Control Register A */
#define TCCR3A _SFR_MEM8(0x90)
/* RegDef: Timer/Counter3 Control Register B */
#define TCCR3B _SFR_MEM8(0x91)
/* RegDef: Timer/Counter3 Control Register C */
#define TCCR3C _SFR_MEM8(0x92)
/* RegDef: Timer/Counter3 Register */
#define TCNT3 _SFR_MEM16(0x94)
#define TCNT3L _SFR_MEM8(0x94)
#define TCNT3H _SFR_MEM8(0x95)
/* RegDef: Timer/Counter3 Input Capture Register */
#define ICR3 _SFR_MEM16(0x96)
#define ICR3L _SFR_MEM8(0x96)
#define ICR3H _SFR_MEM8(0x97)
/* RegDef: Timer/Counter3 Output Compare Register A */
#define OCR3A _SFR_MEM16(0x98)
#define OCR3AL _SFR_MEM8(0x98)
#define OCR3AH _SFR_MEM8(0x99)
/* RegDef: Timer/Counter3 Output Compare Register B */
#define OCR3B _SFR_MEM16(0x9A)
#define OCR3BL _SFR_MEM8(0x9A)
#define OCR3BH _SFR_MEM8(0x9B)
/* RegDef: Timer/Counter3 Output Compare Register C */
#define OCR3C _SFR_MEM16(0x9C)
#define OCR3CL _SFR_MEM8(0x9C)
#define OCR3CH _SFR_MEM8(0x9D)
/* RegDef: Timer/Counter2 Control Register A */
#define TCCR2A _SFR_MEM8(0xB0)
/* RegDef: Timer/Counter2 Register */
#define TCNT2 _SFR_MEM8(0xB2)
/* RegDef: Timer/Counter2 Output Compare Register */
#define OCR2A _SFR_MEM8(0xB3)
/* RegDef: Asynchronous Status Register */
#define ASSR _SFR_MEM8(0xB6)
/* RegDef: TWI Bit Rate Register */
#define TWBR _SFR_MEM8(0xB8)
/* RegDef: TWI Status Register */
#define TWSR _SFR_MEM8(0xB9)
/* RegDef: TWI (Slave) Address Register */
#define TWAR _SFR_MEM8(0xBA)
/* RegDef: TWI Data Register */
#define TWDR _SFR_MEM8(0xBB)
/* RegDef: TWI Control Register */
#define TWCR _SFR_MEM8(0xBC)
/* RegDef: USART0 Control and Status Register A */
#define UCSR0A _SFR_MEM8(0xC0)
/* RegDef: USART0 Control and Status Register B */
#define UCSR0B _SFR_MEM8(0xC1)
/* RegDef: USART0 Control and Status Register C */
#define UCSR0C _SFR_MEM8(0xC2)
/* RegDef: USART0 Baud Rate Register */
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0H _SFR_MEM8(0xC5)
/* RegDef: USART0 I/O Data Register */
#define UDR0 _SFR_MEM8(0xC6)
/* RegDef: USART1 Control and Status Register A */
#define UCSR1A _SFR_MEM8(0xC8)
/* RegDef: USART1 Control and Status Register B */
#define UCSR1B _SFR_MEM8(0xC9)
/* RegDef: USART1 Control and Status Register C */
#define UCSR1C _SFR_MEM8(0xCA)
/* RegDef: USART1 Baud Rate Register */
#define UBRR1 _SFR_MEM16(0xCC)
#define UBRR1L _SFR_MEM8(0xCC)
#define UBRR1H _SFR_MEM8(0xCD)
/* RegDef: USART1 I/O Data Register */
#define UDR1 _SFR_MEM8(0xCE)
/* RegDef: CAN General Control Register*/
#define CANGCON _SFR_MEM8(0xD8)
/* RegDef: CAN General Status Register*/
#define CANGSTA _SFR_MEM8(0xD9)
/* RegDef: CAN General Interrupt Register*/
#define CANGIT _SFR_MEM8(0xDA)
/* RegDef: CAN General Interrupt Enable Register*/
#define CANGIE _SFR_MEM8(0xDB)
/* Word Definition: CAN Enable MOb Register*/
#define CANEN _SFR_MEM16(0xDC)
/* RegDef: CAN Enable MOb Register*/
#define CANEN2 _SFR_MEM8(0xDC)
/* RegDef: CAN Enable MOb Register*/
#define CANEN1 _SFR_MEM8(0xDD)
/* Word Definition: CAN Enable Interrupt MOb Register*/
#define CANIE _SFR_MEM16(0xDE)
/* RegDef: CAN Enable Interrupt MOb Register*/
#define CANIE2 _SFR_MEM8(0xDE)
/* RegDef: CAN Enable Interrupt MOb Register*/
#define CANIE1 _SFR_MEM8(0xDF)
/* RegDef: CAN Status Interrupt MOb Register*/
/*
* WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT
* register.
*/
#define CANSIT _SFR_MEM16(0xE0)
#define CANSIT2 _SFR_MEM8(0xE0)
#define CANSIT1 _SFR_MEM8(0xE1)
/* RegDef: CAN Bit Timing Register 1*/
#define CANBT1 _SFR_MEM8(0xE2)
/* RegDef: CAN Bit Timing Register 2*/
#define CANBT2 _SFR_MEM8(0xE3)
/* RegDef: CAN Bit Timing Register 3*/
#define CANBT3 _SFR_MEM8(0xE4)
/* RegDef: CAN Timer Control Register*/
#define CANTCON _SFR_MEM8(0xE5)
/* RegDef: CAN Timer Register*/
#define CANTIM _SFR_MEM16(0xE6)
#define CANTIML _SFR_MEM8(0xE6)
#define CANTIMH _SFR_MEM8(0xE7)
/* RegDef: CAN TTC Timer Register*/
#define CANTTC _SFR_MEM16(0xE8)
#define CANTTCL _SFR_MEM8(0xE8)
#define CANTTCH _SFR_MEM8(0xE9)
/* RegDef: CAN Transmitt Error Counter Register*/
#define CANTEC _SFR_MEM8(0xEA)
/* RegDef: CAN Receive Error Counter Register*/
#define CANREC _SFR_MEM8(0xEB)
/* RegDef: CAN Highest Priority MOb Register*/
#define CANHPMOB _SFR_MEM8(0xEC)
/* RegDef: CAN Page MOb Register*/
#define CANPAGE _SFR_MEM8(0xED)
/* RegDef: CAN MOb Status Register*/
#define CANSTMOB _SFR_MEM8(0xEE)
/* RegDef: CAN MOb Control and DLC Register*/
#define CANCDMOB _SFR_MEM8(0xEF)
/* RegDef: CAN Identifier Tag Registers*/
#define CANIDT _SFR_MEM32(0xF0)
#define CANIDT4 _SFR_MEM8(0xF0)
#define CANIDT3 _SFR_MEM8(0xF1)
#define CANIDT2 _SFR_MEM8(0xF2)
#define CANIDT1 _SFR_MEM8(0xF3)
/* RegDef: CAN Identifier Mask Registers */
#define CANIDM _SFR_MEM32(0xF4)
#define CANIDM4 _SFR_MEM8(0xF4)
#define CANIDM3 _SFR_MEM8(0xF5)
#define CANIDM2 _SFR_MEM8(0xF6)
#define CANIDM1 _SFR_MEM8(0xF7)
/* RegDef: CAN TTC Timer Register*/
#define CANSTM _SFR_MEM16(0xF8)
#define CANSTML _SFR_MEM8(0xF8)
#define CANSTMH _SFR_MEM8(0xF9)
/* RegDef: CAN Message Register*/
#define CANMSG _SFR_MEM8(0xFA)
/* Interrupt vectors */
/* External Interrupt Request 0 */
#define INT0_vect_num 1
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt Request 1 */
#define INT1_vect_num 2
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* External Interrupt Request 2 */
#define INT2_vect_num 3
#define INT2_vect _VECTOR(3)
#define SIG_INTERRUPT2 _VECTOR(3)
/* External Interrupt Request 3 */
#define INT3_vect_num 4
#define INT3_vect _VECTOR(4)
#define SIG_INTERRUPT3 _VECTOR(4)
/* External Interrupt Request 4 */
#define INT4_vect_num 5
#define INT4_vect _VECTOR(5)
#define SIG_INTERRUPT4 _VECTOR(5)
/* External Interrupt Request 5 */
#define INT5_vect_num 6
#define INT5_vect _VECTOR(6)
#define SIG_INTERRUPT5 _VECTOR(6)
/* External Interrupt Request 6 */
#define INT6_vect_num 7
#define INT6_vect _VECTOR(7)
#define SIG_INTERRUPT6 _VECTOR(7)
/* External Interrupt Request 7 */
#define INT7_vect_num 8
#define INT7_vect _VECTOR(8)
#define SIG_INTERRUPT7 _VECTOR(8)
/* Timer/Counter2 Compare Match */
#define TIMER2_COMP_vect_num 9
#define TIMER2_COMP_vect _VECTOR(9)
#define SIG_OUTPUT_COMPARE2 _VECTOR(9)
/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect_num 10
#define TIMER2_OVF_vect _VECTOR(10)
#define SIG_OVERFLOW2 _VECTOR(10)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect_num 11
#define TIMER1_CAPT_vect _VECTOR(11)
#define SIG_INPUT_CAPTURE1 _VECTOR(11)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect_num 12
#define TIMER1_COMPA_vect _VECTOR(12)
#define SIG_OUTPUT_COMPARE1A _VECTOR(12)
/* Timer/Counter Compare Match B */
#define TIMER1_COMPB_vect_num 13
#define TIMER1_COMPB_vect _VECTOR(13)
#define SIG_OUTPUT_COMPARE1B _VECTOR(13)
/* Timer/Counter1 Compare Match C */
#define TIMER1_COMPC_vect_num 14
#define TIMER1_COMPC_vect _VECTOR(14)
#define SIG_OUTPUT_COMPARE1C _VECTOR(14)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect_num 15
#define TIMER1_OVF_vect _VECTOR(15)
#define SIG_OVERFLOW1 _VECTOR(15)
/* Timer/Counter0 Compare Match */
#define TIMER0_COMP_vect_num 16
#define TIMER0_COMP_vect _VECTOR(16)
#define SIG_OUTPUT_COMPARE0 _VECTOR(16)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect_num 17
#define TIMER0_OVF_vect _VECTOR(17)
#define SIG_OVERFLOW0 _VECTOR(17)
/* CAN Transfer Complete or Error */
#define CANIT_vect_num 18
#define CANIT_vect _VECTOR(18)
#define SIG_CAN_INTERRUPT1 _VECTOR(18)
/* CAN Timer Overrun */
#define OVRIT_vect_num 19
#define OVRIT_vect _VECTOR(19)
#define SIG_CAN_OVERFLOW1 _VECTOR(19)
/* SPI Serial Transfer Complete */
#define SPI_STC_vect_num 20
#define SPI_STC_vect _VECTOR(20)
#define SIG_SPI _VECTOR(20)
/* USART0, Rx Complete */
#define USART0_RX_vect_num 21
#define USART0_RX_vect _VECTOR(21)
#define SIG_UART0_RECV _VECTOR(21)
#define SIG_USART0_RECV _VECTOR(21)
/* USART0 Data Register Empty */
#define USART0_UDRE_vect_num 22
#define USART0_UDRE_vect _VECTOR(22)
#define SIG_UART0_DATA _VECTOR(22)
#define SIG_USART0_DATA _VECTOR(22)
/* USART0, Tx Complete */
#define USART0_TX_vect_num 23
#define USART0_TX_vect _VECTOR(23)
#define SIG_UART0_TRANS _VECTOR(23)
#define SIG_USART0_TRANS _VECTOR(23)
/* Analog Comparator */
#define ANALOG_COMP_vect_num 24
#define ANALOG_COMP_vect _VECTOR(24)
#define SIG_COMPARATOR _VECTOR(24)
/* ADC Conversion Complete */
#define ADC_vect_num 25
#define ADC_vect _VECTOR(25)
#define SIG_ADC _VECTOR(25)
/* EEPROM Ready */
#define EE_READY_vect_num 26
#define EE_READY_vect _VECTOR(26)
#define SIG_EEPROM_READY _VECTOR(26)
/* Timer/Counter3 Capture Event */
#define TIMER3_CAPT_vect_num 27
#define TIMER3_CAPT_vect _VECTOR(27)
#define SIG_INPUT_CAPTURE3 _VECTOR(27)
/* Timer/Counter3 Compare Match A */
#define TIMER3_COMPA_vect_num 28
#define TIMER3_COMPA_vect _VECTOR(28)
#define SIG_OUTPUT_COMPARE3A _VECTOR(28)
/* Timer/Counter3 Compare Match B */
#define TIMER3_COMPB_vect_num 29
#define TIMER3_COMPB_vect _VECTOR(29)
#define SIG_OUTPUT_COMPARE3B _VECTOR(29)
/* Timer/Counter3 Compare Match C */
#define TIMER3_COMPC_vect_num 30
#define TIMER3_COMPC_vect _VECTOR(30)
#define SIG_OUTPUT_COMPARE3C _VECTOR(30)
/* Timer/Counter3 Overflow */
#define TIMER3_OVF_vect_num 31
#define TIMER3_OVF_vect _VECTOR(31)
#define SIG_OVERFLOW3 _VECTOR(31)
/* USART1, Rx Complete */
#define USART1_RX_vect_num 32
#define USART1_RX_vect _VECTOR(32)
#define SIG_UART1_RECV _VECTOR(32)
#define SIG_USART1_RECV _VECTOR(32)
/* USART1, Data Register Empty */
#define USART1_UDRE_vect_num 33
#define USART1_UDRE_vect _VECTOR(33)
#define SIG_UART1_DATA _VECTOR(33)
#define SIG_USART1_DATA _VECTOR(33)
/* USART1, Tx Complete */
#define USART1_TX_vect_num 34
#define USART1_TX_vect _VECTOR(34)
#define SIG_UART1_TRANS _VECTOR(34)
#define SIG_USART1_TRANS _VECTOR(34)
/* 2-wire Serial Interface */
#define TWI_vect_num 35
#define TWI_vect _VECTOR(35)
#define SIG_2WIRE_SERIAL _VECTOR(35)
/* Store Program Memory Read */
#define SPM_READY_vect_num 36
#define SPM_READY_vect _VECTOR(36)
#define SIG_SPM_READY _VECTOR(36)
#define _VECTORS_SIZE 148
/* The Register Bit names are represented by their bit number (0-7). */
/* Register Bits [ASSR] */
/* Asynchronous Status Register */
#define EXCLK 4
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0
/* End Register Bits */
/* Register Bits [TWCR] */
/* 2-wire Control Register - TWCR */
#define TWINT 7
#define TWEA 6
#define TWSTA 5
#define TWSTO 4
#define TWWC 3
#define TWEN 2
#define TWIE 0
/* End Register Bits */
/* Register Bits [TWAR] */
/* 2-wire Address Register - TWAR */
#define TWA6 7
#define TWA5 6
#define TWA4 5
#define TWA3 4
#define TWA2 3
#define TWA1 2
#define TWA0 1
#define TWGCE 0
/* End Register Bits */
/* Register Bits [TWSR] */
/* 2-wire Status Register - TWSR */
#define TWS7 7
#define TWS6 6
#define TWS5 5
#define TWS4 4
#define TWS3 3
#define TWPS1 1
#define TWPS0 0
/* End Register Bits */
/* Register Bits [XMCRB] */
/* External Memory Control Register B - XMCRB */
#define XMBK 7
#define XMM2 2
#define XMM1 1
#define XMM0 0
/* End Register Bits */
/* Register Bits [XMCRA] */
/* External Memory Control Register A - XMCRA */
#define SRE 7
#define SRL2 6
#define SRL1 5
#define SRL0 4
#define SRW11 3
#define SRW10 2
#define SRW01 1
#define SRW00 0
/* End Register Bits */
/* Register Bits [RAMPZ] */
/* RAM Page Z select register - RAMPZ */
#define RAMPZ0 0
/* End Register Bits */
/* Register Bits [EICRA] */
/* External Interrupt Control Register A - EICRA */
#define ISC31 7
#define ISC30 6
#define ISC21 5
#define ISC20 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* End Register Bits */
/* Register Bits [EICRB] */
/* External Interrupt Control Register B - EICRB */
#define ISC71 7
#define ISC70 6
#define ISC61 5
#define ISC60 4
#define ISC51 3
#define ISC50 2
#define ISC41 1
#define ISC40 0
/* End Register Bits */
/* Register Bits [SPMCSR] */
/* Store Program Memory Control Register - SPMCSR, SPMCR */
#define SPMIE 7
#define RWWSB 6
#define RWWSRE 4
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0
/* End Register Bits */
/* Register Bits [EIMSK] */
/* External Interrupt MaSK register - EIMSK */
#define INT7 7
#define INT6 6
#define INT5 5
#define INT4 4
#define INT3 3
#define INT2 2
#define INT1 1
#define INT0 0
/* End Register Bits */
/* Register Bits [EIFR] */
/* External Interrupt Flag Register - EIFR */
#define INTF7 7
#define INTF6 6
#define INTF5 5
#define INTF4 4
#define INTF3 3
#define INTF2 2
#define INTF1 1
#define INTF0 0
/* End Register Bits */
/* Register Bits [TCCR2] */
/* Timer/Counter 2 Control Register - TCCR2 */
#define FOC2A 7
#define WGM20 6
#define COM2A1 5
#define COM2A0 4
#define WGM21 3
#define CS22 2
#define CS21 1
#define CS20 0
/* End Register Bits */
/* Register Bits [TCCR1A] */
/* Timer/Counter 1 Control and Status Register A - TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define COM1C1 3
#define COM1C0 2
#define WGM11 1
#define WGM10 0
/* End Register Bits */
/* Register Bits [TCCR3A] */
/* Timer/Counter 3 Control and Status Register A - TCCR3A */
#define COM3A1 7
#define COM3A0 6
#define COM3B1 5
#define COM3B0 4
#define COM3C1 3
#define COM3C0 2
#define WGM31 1
#define WGM30 0
/* End Register Bits */
/* Register Bits [TCCR1B] */
/* Timer/Counter 1 Control and Status Register B - TCCR1B */
#define ICNC1 7
#define ICES1 6
#define WGM13 4
#define WGM12 3
#define CS12 2
#define CS11 1
#define CS10 0
/* End Register Bits */
/* Register Bits [TCCR3B] */
/* Timer/Counter 3 Control and Status Register B - TCCR3B */
#define ICNC3 7
#define ICES3 6
#define WGM33 4
#define WGM32 3
#define CS32 2
#define CS31 1
#define CS30 0
/* End Register Bits */
/* Register Bits [TCCR3C] */
/* Timer/Counter 3 Control Register C - TCCR3C */
#define FOC3A 7
#define FOC3B 6
#define FOC3C 5
/* End Register Bits */
/* Register Bits [TCCR1C] */
/* Timer/Counter 1 Control Register C - TCCR1C */
#define FOC1A 7
#define FOC1B 6
#define FOC1C 5
/* End Register Bits */
/* Register Bits [OCDR] */
/* On-chip Debug Register - OCDR */
#define IDRD 7
#define OCDR7 7
#define OCDR6 6
#define OCDR5 5
#define OCDR4 4
#define OCDR3 3
#define OCDR2 2
#define OCDR1 1
#define OCDR0 0
/* End Register Bits */
/* Register Bits [WDTCR] */
/* Watchdog Timer Control Register - WDTCR */
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* End Register Bits */
/* Register Bits [SPSR] */
/* SPI Status Register - SPSR */
#define SPIF 7
#define WCOL 6
#define SPI2X 0
/* End Register Bits */
/* Register Bits [SPCR] */
/* SPI Control Register - SPCR */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* End Register Bits */
/* Register Bits [UCSR1C] */
/* USART1 Register C - UCSR1C */
#define UMSEL1 6
#define UPM11 5
#define UPM10 4
#define USBS1 3
#define UCSZ11 2
#define UCSZ10 1
#define UCPOL1 0
/* End Register Bits */
/* Register Bits [UCSR0C] */
/* USART0 Register C - UCSR0C */
#define UMSEL0 6
#define UPM01 5
#define UPM00 4
#define USBS0 3
#define UCSZ01 2
#define UCSZ00 1
#define UCPOL0 0
/* End Register Bits */
/* Register Bits [UCSR1A] */
/* USART1 Status Register A - UCSR1A */
#define RXC1 7
#define TXC1 6
#define UDRE1 5
#define FE1 4
#define DOR1 3
#define UPE1 2
#define U2X1 1
#define MPCM1 0
/* End Register Bits */
/* Register Bits [UCSR0A] */
/* USART0 Status Register A - UCSR0A */
#define RXC0 7
#define TXC0 6
#define UDRE0 5
#define FE0 4
#define DOR0 3
#define UPE0 2
#define U2X0 1
#define MPCM0 0
/* End Register Bits */
/* Register Bits [UCSR1B] */
/* USART1 Control Register B - UCSR1B */
#define RXCIE1 7
#define TXCIE1 6
#define UDRIE1 5
#define RXEN1 4
#define TXEN1 3
#define UCSZ12 2
#define RXB81 1
#define TXB81 0
/* End Register Bits */
/* Register Bits [UCSR0B] */
/* USART0 Control Register B - UCSR0B */
#define RXCIE0 7
#define TXCIE0 6
#define UDRIE0 5
#define RXEN0 4
#define TXEN0 3
#define UCSZ02 2
#define RXB80 1
#define TXB80 0
/* End Register Bits */
/* Register Bits [ACSR] */
/* Analog Comparator Control and Status Register - ACSR */
#define ACD 7
#define ACBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* End Register Bits */
/* Register Bits [ADCSRA] */
/* ADC Control and status register - ADCSRA */
#define ADEN 7
#define ADSC 6
#define ADATE 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* End Register Bits */
/*
The ADHSM bit has been removed from all documentation,
as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.