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[Feature] Multi demension for loop #567
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This is a nice idea. I think veryl should also support iterators (and type inference), so in addition to what you have listed:
This way, there are no accidental mistakes where, for example, the dimensions of |
SystemVerilog doens not support There are two way fot this.
int a[2][3];
for (int i = 0, int j = 0; (i < 2) && (j < 3); i += ((j == 2) ? 1 : 0), j += ((j == 2) ? -2 : 1)) begin
$display("a[%0d][%0d] = %0d", i, j, a[i][j]);
end I've confirmed that three major simulators support this notation but I'm not sure synthesis tools do.
int a[2][3][4];
for (int i_j_k = 0; i_j_k < (2 * 3 * 4); i_j_k++) begin
automatic int k = (i_j_k / 1) % 4;
automatic int j = (i_j_k / 4) % 3;
automatic int i = (i_j_k / 12) % 2;
$display("a[%0d][%0d][%0d] = %0d", i, j, k, a[i][j][k]);
end |
Which syntex do you prefer? for i: u32 in 0..10, j: u32 in 0..20 {
...
} for i: u32, j: u32 in 0..10, 0..20 {
...
} |
SystemVerilog provides foreach statement to iterate an array and the
foreach
statement can iterate a single dimension array only but also a multi dimension array.To support this feature on Veryl, I'd like to extend
for
statement to take multiple iterator.The text was updated successfully, but these errors were encountered: