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FPGA_Genome_Alignment
FPGA_Genome_Alignment PublicForked from sgauthamr2001/FPGA_Genome_Alignment
Hardware Acceleration of Banded Smith-Waterman Algorithm on an FPGA using Systolic array based architecture.
Verilog
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Self_Attention_Accelerator
Self_Attention_Accelerator PublicHardware Accelerator for Self Attention Layer in Bluespec - for Shakti C Class
Bluespec
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MNIST_picoRV32
MNIST_picoRV32 PublicForked from sgauthamr2001/MNIST_picoRV32
Hardware Acceleration of a 2-layer integer quantised Neural Network trained on MNIST dataset.
Verilog
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CFU-Playground
CFU-Playground PublicForked from google/CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).
Verilog
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Microprocessor-Theory-Lab
Microprocessor-Theory-Lab PublicEE2016 Microprocessors, IIT Madras (Jul-Nov 2020)
Assembly
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Deep-Learning-Assignment
Deep-Learning-Assignment PublicElectronics Club, IIT Madras 2021-2022
Jupyter Notebook 1
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