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x86cpuid.h
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x86cpuid.h
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/*********************************************************
* Copyright (c) 1998-2023 Broadcom. All Rights Reserved.
* The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation version 2.1 and no later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the Lesser GNU General Public
* License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
*********************************************************/
/*********************************************************
* The contents of this file are subject to the terms of the Common
* Development and Distribution License (the "License") version 1.0
* and no later version. You may not use this file except in
* compliance with the License.
*
* You can obtain a copy of the License at
* http://www.opensource.org/licenses/cddl1.php
*
* See the License for the specific language governing permissions
* and limitations under the License.
*
*********************************************************/
#ifndef _X86CPUID_H_
#define _X86CPUID_H_
/* http://www.sandpile.org/ia32/cpuid.htm */
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMX
#define INCLUDE_ALLOW_VMKERNEL
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_DISTRIBUTE
#define INCLUDE_ALLOW_VMK_MODULE
#define INCLUDE_ALLOW_VMCORE
#define INCLUDE_ALLOW_VMMON
#include "includeCheck.h"
#include "vm_basic_types.h"
#include "community_source.h"
#include "x86vendor.h"
#include "vm_assert.h"
#if defined __cplusplus
extern "C" {
#endif
/*
* The linux kernel's ptrace.h stupidly defines the bare
* EAX/EBX/ECX/EDX, which wrecks havoc with our preprocessor tricks.
*/
#undef EAX
#undef EBX
#undef ECX
#undef EDX
typedef struct CPUIDRegs {
uint32 eax, ebx, ecx, edx;
} CPUIDRegs;
typedef union CPUIDRegsUnion {
uint32 array[4];
CPUIDRegs regs;
uint64 force8byteAlign[2]; /* See CpuidInfoNodePtr (needed on Apple Mac). */
} CPUIDRegsUnion;
/*
* Results of calling cpuid(eax, ecx) on all host logical CPU.
*/
#ifdef _MSC_VER
// TODO: Move this under the push
#pragma warning (disable :4200) // non-std extension: zero-sized array in struct
#pragma warning (push)
#pragma warning (disable :4100) // unreferenced parameters
#endif
#if defined VMKERNEL || (!defined(__FreeBSD__) && !defined(__sun__))
/*
* FreeBSD and Solaris do not support pragma pack until gcc-4.6,
* but do not need these structures (which are part of vmmon).
* Vmkernel sets __FreeBSD__ for a few files.
*/
#pragma pack(push, 1)
typedef struct CPUIDReply {
/*
* Unique host logical CPU identifier. It does not change across queries, so
* we use it to correlate the replies of multiple queries.
*/
uint64 tag; // OUT
CPUIDRegs regs; // OUT
} CPUIDReply;
typedef struct CPUIDQuery {
uint32 eax; // IN
uint32 ecx; // IN
uint32 numLogicalCPUs; // IN/OUT
CPUIDReply logicalCPUs[0]; // OUT
} CPUIDQuery;
#pragma pack(pop)
#endif
/*
* Table of known CPUID levels.
*
* The first parameter defines whether the level has its default masks
* generated from the values in this file. Any level which is marked as FALSE
* here *must* have all monitor support types set to NA. A static assert in
* lib/cpuidcompat/cpuidcompat.c will check this.
*
* The second parameter is the "short name" of the level. It's mainly used for
* token concatenation in various macros.
*
* The third parameter is the actual numeric value of that level (the EAX input
* value).
*
* The fourth parameter is a "subleaf count", where 0 means that ecx is
* ignored, otherwise is the count of sub-leaves.
*
* The fifth parameter is the first hardware version that is *aware* of the
* CPUID level (0 = existed since dawn of time), even though we may not expose
* this level or parts of it to guest.
*/
/* MASKS, LVL, VAL, CNT, HWV */
#define CPUID_KNOWN_LEVELS \
CPUIDLEVEL(TRUE, 0, 0x0, 0, 0) \
CPUIDLEVEL(TRUE, 1, 0x1, 0, 0) \
CPUIDLEVEL(FALSE, 2, 0x2, 0, 0) \
CPUIDLEVEL(FALSE, 4, 0x4, 7, 0) \
CPUIDLEVEL(FALSE, 5, 0x5, 0, 0) \
CPUIDLEVEL(TRUE, 6, 0x6, 0, 0) \
CPUIDLEVEL(TRUE, 7, 0x7, 3, 0) \
CPUIDLEVEL(TRUE, 9, 0x9, 0, 17) \
CPUIDLEVEL(FALSE, A, 0xa, 0, 0) \
CPUIDLEVEL(FALSE, B, 0xb, 3, 0) \
CPUIDLEVEL(TRUE, D, 0xd, 19, 0) \
CPUIDLEVEL(TRUE, F, 0xf, 2, 13) \
CPUIDLEVEL(TRUE, 10, 0x10, 4, 13) \
CPUIDLEVEL(TRUE, 12, 0x12, 4, 13) \
CPUIDLEVEL(TRUE, 14, 0x14, 2, 13) \
CPUIDLEVEL(TRUE, 15, 0x15, 0, 13) \
CPUIDLEVEL(TRUE, 16, 0x16, 0, 13) \
CPUIDLEVEL(TRUE, 17, 0x17, 4, 14) \
CPUIDLEVEL(TRUE, 18, 0x18, 8, 17) \
CPUIDLEVEL(TRUE, 19, 0x19, 0, 20) \
CPUIDLEVEL(TRUE, 1A, 0x1a, 0, 17) \
CPUIDLEVEL(TRUE, 1B, 0x1b, 2, 17) \
CPUIDLEVEL(TRUE, 1C, 0x1c, 0, 20) \
CPUIDLEVEL(TRUE, 1D, 0x1d, 2, 19) \
CPUIDLEVEL(TRUE, 1E, 0x1e, 1, 19) \
CPUIDLEVEL(FALSE, 1F, 0x1f, 6, 17) \
CPUIDLEVEL(TRUE, 20, 0x20, 1, 20) \
CPUIDLEVEL(TRUE, 21, 0x21, 1, 20) \
CPUIDLEVEL(TRUE, 23, 0x23, 4, 21) \
CPUIDLEVEL(FALSE, 400, 0x40000000, 0, 0) \
CPUIDLEVEL(FALSE, 401, 0x40000001, 0, 0) \
CPUIDLEVEL(FALSE, 402, 0x40000002, 0, 0) \
CPUIDLEVEL(FALSE, 403, 0x40000003, 0, 0) \
CPUIDLEVEL(FALSE, 404, 0x40000004, 0, 0) \
CPUIDLEVEL(FALSE, 405, 0x40000005, 0, 0) \
CPUIDLEVEL(FALSE, 406, 0x40000006, 0, 0) \
CPUIDLEVEL(FALSE, 410, 0x40000010, 0, 0) \
CPUIDLEVEL(FALSE, 80, 0x80000000, 0, 0) \
CPUIDLEVEL(TRUE, 81, 0x80000001, 0, 0) \
CPUIDLEVEL(FALSE, 82, 0x80000002, 0, 0) \
CPUIDLEVEL(FALSE, 83, 0x80000003, 0, 0) \
CPUIDLEVEL(FALSE, 84, 0x80000004, 0, 0) \
CPUIDLEVEL(FALSE, 85, 0x80000005, 0, 0) \
CPUIDLEVEL(FALSE, 86, 0x80000006, 0, 0) \
CPUIDLEVEL(FALSE, 87, 0x80000007, 0, 0) \
CPUIDLEVEL(TRUE, 88, 0x80000008, 0, 0) \
CPUIDLEVEL(TRUE, 8A, 0x8000000a, 0, 0) \
CPUIDLEVEL(FALSE, 819, 0x80000019, 0, 0) \
CPUIDLEVEL(FALSE, 81A, 0x8000001a, 0, 0) \
CPUIDLEVEL(FALSE, 81B, 0x8000001b, 0, 0) \
CPUIDLEVEL(FALSE, 81C, 0x8000001c, 0, 0) \
CPUIDLEVEL(FALSE, 81D, 0x8000001d, 5, 0) \
CPUIDLEVEL(FALSE, 81E, 0x8000001e, 0, 0) \
CPUIDLEVEL(TRUE, 81F, 0x8000001f, 0, 14) \
CPUIDLEVEL(TRUE, 820, 0x80000020, 4, 17) \
CPUIDLEVEL(TRUE, 821, 0x80000021, 0, 17) \
CPUIDLEVEL(TRUE, 822, 0x80000022, 0, 20) \
CPUIDLEVEL(TRUE, 823, 0x80000023, 0, 20) \
CPUIDLEVEL(FALSE, 826, 0x80000026, 4, 20)
/* Define all CPUID levels in the form: CPUID_LEVEL_<ShortName> */
typedef enum {
#define CPUIDLEVEL(t, s, v, c, h) CPUID_LEVEL_##s,
CPUID_KNOWN_LEVELS
#undef CPUIDLEVEL
CPUID_NUM_KNOWN_LEVELS
} CpuidLevel;
/* Enum to translate between shorthand name and actual CPUID level value. */
enum {
#define CPUIDLEVEL(t, s, v, c, h) CPUID_LEVEL_VAL_##s = v,
CPUID_KNOWN_LEVELS
#undef CPUIDLEVEL
};
/* Named feature leaves */
#define CPUID_FEATURE_INFORMATION 0x01
#define CPUID_PROCESSOR_TOPOLOGY 4
#define CPUID_MWAIT_FEATURES 5
#define CPUID_PMC_FEATURES 0xa
#define CPUID_XSAVE_FEATURES 0xd
#define CPUID_RDT_FEATURES 0x10
#define CPUID_SGX_FEATURES 0x12
#define CPUID_PT_FEATURES 0x14
#define CPUID_HYPERVISOR_LEVEL_0 0x40000000
#define CPUID_VMW_FEATURES 0x40000010
#define CPUID_HYPERVISOR_LEVEL_MAX 0x400000FF
#define CPUID_SVM_FEATURES 0x8000000a
#define CPUID_SEV_INFO 0x8000001f
/*
* CPUID result registers
*/
#define CPUID_REGS \
CPUIDREG(EAX, eax) \
CPUIDREG(EBX, ebx) \
CPUIDREG(ECX, ecx) \
CPUIDREG(EDX, edx)
typedef enum {
#define CPUIDREG(uc, lc) CPUID_REG_##uc,
CPUID_REGS
#undef CPUIDREG
CPUID_NUM_REGS
} CpuidReg;
#define CPUID_INTEL_VENDOR_STRING "GenuntelineI"
#define CPUID_AMD_VENDOR_STRING "AuthcAMDenti"
#define CPUID_CYRIX_VENDOR_STRING "CyriteadxIns"
#define CPUID_VIA_VENDOR_STRING "CentaulsaurH"
#define CPUID_HYGON_VENDOR_STRING "HygouinenGen"
#define CPUID_INTEL_TDX_VENDOR_STRING "Inte lTDX"
#define CPUID_HYPERV_HYPERVISOR_VENDOR_STRING "Microsoft Hv"
#define CPUID_KVM_HYPERVISOR_VENDOR_STRING "KVMKVMKVM\0\0\0"
#define CPUID_VMWARE_HYPERVISOR_VENDOR_STRING "VMwareVMware"
#define CPUID_XEN_HYPERVISOR_VENDOR_STRING "XenVMMXenVMM"
#define CPUID_INTEL_VENDOR_STRING_FIXED "GenuineIntel"
#define CPUID_AMD_VENDOR_STRING_FIXED "AuthenticAMD"
#define CPUID_CYRIX_VENDOR_STRING_FIXED "CyrixInstead"
#define CPUID_VIA_VENDOR_STRING_FIXED "CentaurHauls"
#define CPUID_HYGON_VENDOR_STRING_FIXED "HygonGenuine"
#define CPUID_INTEL_TDX_VENDOR_STRING_FIXED "IntelTDX "
/*
* FIELD can be defined to process the CPUID information provided in the
* following CPUID_FIELD_DATA macro.
*
* The first parameter is the CPUID level of the feature (must be defined in
* CPUID_KNOWN_LEVELS, above).
*
* The second parameter is the CPUID sub-level (subleaf) of the feature. Please
* make sure here the number is consistent with the "subleaf count" in
* CPUIDLEVEL macro. I.e., if a feature is being added to a _new_ subleaf,
* update the subleaf count above as well.
*
* The third parameter is the result register.
*
* The fourth and fifth parameters are the bit position of the field and the
* width, respectively.
*
* The sixth is the name of the field.
*
* The seventh parameter specifies the monitor support characteristics for
* this field. The value must be a valid CpuidFieldSupported value (omitting
* CPUID_FIELD_SUPPORT_ for convenience). The meaning of those values are
* described below.
*
* The eighth parameter specifies the first virtual hardware version that
* implements the field (if 7th field is YES or ANY), or 0 (if 7th field is
* NO or NA). The value FUT means HW_VERSION_FUTURE. The field's hardware
* version must match the version in defaultMasks (cpuidcompat.c) if defined
* there, and must be less than or equal to the version of the cpuid leaf
* it's in.
*
* FLAG is defined identically to FIELD, but its accessors are more appropriate
* for 1-bit flags, and compile-time asserts enforce that the size is 1 bit
* wide.
*/
/*
* CpuidFieldSupported is made up of the following values:
*
* NO: A feature/field that IS NOT SUPPORTED by the monitor. Even
* if the host supports this feature, we will never expose it to
* the guest.
*
* YES: A feature/field that IS SUPPORTED by the monitor. If the
* host supports this feature, we will expose it to the guest. If
* not, then we will not set the feature.
*
* ANY: A feature/field that IS ALWAYS SUPPORTED by the monitor.
* Even if the host does not support the feature, the monitor can
* expose the feature to the guest. As with "YES", the guest cpuid
* value defaults to the host/evc cpuid value. But usually the
* guest cpuid value is recomputed at power on, ignoring the default
* value.
*
* NA: Only legal for levels not masked/tested by default (see
* above for this definition). Such fields must always be marked
* as NA.
*
* These distinctions can be translated into a common CPUID mask string as
* follows:
*
* YES --> "H" (Host). We support the feature, so show it to the
* guest if the host has the feature.
*
* ANY/NA --> "X" (Ignore). By default, don't perform checks for
* this feature bit. Per-GOS masks may choose to set this bit in
* the guest. (e.g. the APIC feature bit is always set to 1.)
*
* See lib/cpuidcompat/cpuidcompat.c for any possible overrides to
* these defaults.
*/
/*
* XSAVEOPT was incorrectly missed until HWv11. See comment for
* DisableReqHWVersion in vmFeatureCPUID.c for more detail.
*/
typedef enum {
CPUID_FIELD_SUPPORTED_NO,
CPUID_FIELD_SUPPORTED_YES,
CPUID_FIELD_SUPPORTED_ANY,
CPUID_FIELD_SUPPORTED_NA,
CPUID_NUM_FIELD_SUPPORTEDS
} CpuidFieldSupported;
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_0 \
FIELD( 0, 0, EAX, 0, 32, NUMLEVELS, ANY, 4 ) \
FIELD( 0, 0, EBX, 0, 32, VENDOR1, YES, 4 ) \
FIELD( 0, 0, ECX, 0, 32, VENDOR3, YES, 4 ) \
FIELD( 0, 0, EDX, 0, 32, VENDOR2, YES, 4 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_1 \
FIELD( 1, 0, EAX, 0, 4, STEPPING, ANY, 4 ) \
FIELD( 1, 0, EAX, 4, 4, MODEL, ANY, 4 ) \
FIELD( 1, 0, EAX, 8, 4, FAMILY, YES, 4 ) \
FIELD( 1, 0, EAX, 12, 2, TYPE, ANY, 4 ) \
FIELD( 1, 0, EAX, 16, 4, EXTENDED_MODEL, ANY, 4 ) \
FIELD( 1, 0, EAX, 20, 8, EXTENDED_FAMILY, YES, 4 ) \
FIELD( 1, 0, EBX, 0, 8, BRAND_ID, ANY, 4 ) \
FIELD( 1, 0, EBX, 8, 8, CLFL_SIZE, ANY, 4 ) \
FIELD( 1, 0, EBX, 16, 8, LCPU_COUNT, ANY, 4 ) \
FIELD( 1, 0, EBX, 24, 8, APICID, ANY, 4 ) \
FLAG( 1, 0, ECX, 0, 1, SSE3, YES, 4 ) \
FLAG( 1, 0, ECX, 1, 1, PCLMULQDQ, YES, 4 ) \
FLAG( 1, 0, ECX, 2, 1, DTES64, NO, 0 ) \
FLAG( 1, 0, ECX, 3, 1, MWAIT, YES, 7 ) \
FLAG( 1, 0, ECX, 4, 1, DSCPL, NO, 0 ) \
FLAG( 1, 0, ECX, 5, 1, VMX, YES, 8 ) \
FLAG( 1, 0, ECX, 6, 1, SMX, YES, FUT ) \
FLAG( 1, 0, ECX, 7, 1, EIST, NO, 0 ) \
FLAG( 1, 0, ECX, 8, 1, TM2, NO, 0 ) \
FLAG( 1, 0, ECX, 9, 1, SSSE3, YES, 4 ) \
FLAG( 1, 0, ECX, 10, 1, CNXTID, NO, 0 ) \
FLAG( 1, 0, ECX, 11, 1, SDBG, NO, 0 ) \
FLAG( 1, 0, ECX, 12, 1, FMA, YES, 8 ) \
FLAG( 1, 0, ECX, 13, 1, CMPXCHG16B, YES, 4 ) \
FLAG( 1, 0, ECX, 14, 1, xTPR, NO, 0 ) \
FLAG( 1, 0, ECX, 15, 1, PDCM, NO, 0 ) \
FLAG( 1, 0, ECX, 17, 1, PCID, YES, 9 ) \
FLAG( 1, 0, ECX, 18, 1, DCA, NO, 0 ) \
FLAG( 1, 0, ECX, 19, 1, SSE41, YES, 4 ) \
FLAG( 1, 0, ECX, 20, 1, SSE42, YES, 4 ) \
FLAG( 1, 0, ECX, 21, 1, x2APIC, ANY, 9 ) \
FLAG( 1, 0, ECX, 22, 1, MOVBE, YES, 4 ) \
FLAG( 1, 0, ECX, 23, 1, POPCNT, YES, 4 ) \
FLAG( 1, 0, ECX, 24, 1, TSC_DEADLINE, ANY, 11 ) \
FLAG( 1, 0, ECX, 25, 1, AES, YES, 4 ) \
FLAG( 1, 0, ECX, 26, 1, XSAVE, YES, 8 ) \
FLAG( 1, 0, ECX, 27, 1, OSXSAVE, ANY, 8 ) \
FLAG( 1, 0, ECX, 28, 1, AVX, YES, 8 ) \
FLAG( 1, 0, ECX, 29, 1, F16C, YES, 9 ) \
FLAG( 1, 0, ECX, 30, 1, RDRAND, YES, 9 ) \
FLAG( 1, 0, ECX, 31, 1, HYPERVISOR, ANY, 4 ) \
FLAG( 1, 0, EDX, 0, 1, FPU, YES, 4 ) \
FLAG( 1, 0, EDX, 1, 1, VME, YES, 4 ) \
FLAG( 1, 0, EDX, 2, 1, DE, YES, 4 ) \
FLAG( 1, 0, EDX, 3, 1, PSE, YES, 4 ) \
FLAG( 1, 0, EDX, 4, 1, TSC, YES, 4 ) \
FLAG( 1, 0, EDX, 5, 1, MSR, YES, 4 ) \
FLAG( 1, 0, EDX, 6, 1, PAE, YES, 4 ) \
FLAG( 1, 0, EDX, 7, 1, MCE, YES, 4 ) \
FLAG( 1, 0, EDX, 8, 1, CX8, YES, 4 ) \
FLAG( 1, 0, EDX, 9, 1, APIC, ANY, 4 ) \
FLAG( 1, 0, EDX, 11, 1, SEP, YES, 4 ) \
FLAG( 1, 0, EDX, 12, 1, MTRR, YES, 4 ) \
FLAG( 1, 0, EDX, 13, 1, PGE, YES, 4 ) \
FLAG( 1, 0, EDX, 14, 1, MCA, YES, 4 ) \
FLAG( 1, 0, EDX, 15, 1, CMOV, YES, 4 ) \
FLAG( 1, 0, EDX, 16, 1, PAT, YES, 4 ) \
FLAG( 1, 0, EDX, 17, 1, PSE36, YES, 4 ) \
FLAG( 1, 0, EDX, 18, 1, PSN, YES, 4 ) \
FLAG( 1, 0, EDX, 19, 1, CLFSH, YES, 4 ) \
FLAG( 1, 0, EDX, 21, 1, DS, YES, 4 ) \
FLAG( 1, 0, EDX, 22, 1, ACPI, ANY, 4 ) \
FLAG( 1, 0, EDX, 23, 1, MMX, YES, 4 ) \
FLAG( 1, 0, EDX, 24, 1, FXSR, YES, 4 ) \
FLAG( 1, 0, EDX, 25, 1, SSE, YES, 4 ) \
FLAG( 1, 0, EDX, 26, 1, SSE2, YES, 4 ) \
FLAG( 1, 0, EDX, 27, 1, SS, YES, 4 ) \
FLAG( 1, 0, EDX, 28, 1, HTT, ANY, 7 ) \
FLAG( 1, 0, EDX, 29, 1, TM, NO, 0 ) \
FLAG( 1, 0, EDX, 30, 1, IA64, NO, 0 ) \
FLAG( 1, 0, EDX, 31, 1, PBE, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_2 \
FIELD( 2, 0, EAX, 0, 8, LEAF2_COUNT, NA, 0 ) \
FIELD( 2, 0, EAX, 8, 8, LEAF2_CACHE1, NA, 0 ) \
FIELD( 2, 0, EAX, 16, 8, LEAF2_CACHE2, NA, 0 ) \
FIELD( 2, 0, EAX, 24, 8, LEAF2_CACHE3, NA, 0 ) \
FIELD( 2, 0, EBX, 0, 8, LEAF2_CACHE4, NA, 0 ) \
FIELD( 2, 0, EBX, 8, 8, LEAF2_CACHE5, NA, 0 ) \
FIELD( 2, 0, EBX, 16, 8, LEAF2_CACHE6, NA, 0 ) \
FIELD( 2, 0, EBX, 24, 8, LEAF2_CACHE7, NA, 0 ) \
FIELD( 2, 0, ECX, 0, 8, LEAF2_CACHE8, NA, 0 ) \
FIELD( 2, 0, ECX, 8, 8, LEAF2_CACHE9, NA, 0 ) \
FIELD( 2, 0, ECX, 16, 8, LEAF2_CACHE10, NA, 0 ) \
FIELD( 2, 0, ECX, 24, 8, LEAF2_CACHE11, NA, 0 ) \
FIELD( 2, 0, EDX, 0, 8, LEAF2_CACHE12, NA, 0 ) \
FIELD( 2, 0, EDX, 8, 8, LEAF2_CACHE13, NA, 0 ) \
FIELD( 2, 0, EDX, 16, 8, LEAF2_CACHE14, NA, 0 ) \
FIELD( 2, 0, EDX, 24, 8, LEAF2_CACHE15, NA, 0 ) \
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_4 \
FIELD( 4, 0, EAX, 0, 5, LEAF4_CACHE_TYPE, NA, 0 ) \
FIELD( 4, 0, EAX, 5, 3, LEAF4_CACHE_LEVEL, NA, 0 ) \
FLAG( 4, 0, EAX, 8, 1, LEAF4_CACHE_SELF_INIT, NA, 0 ) \
FLAG( 4, 0, EAX, 9, 1, LEAF4_CACHE_FULLY_ASSOC, NA, 0 ) \
FIELD( 4, 0, EAX, 14, 12, LEAF4_CACHE_NUMHT_SHARING, NA, 0 ) \
FIELD( 4, 0, EAX, 26, 6, LEAF4_CORE_COUNT, NA, 0 ) \
FIELD( 4, 0, EBX, 0, 12, LEAF4_CACHE_LINE, NA, 0 ) \
FIELD( 4, 0, EBX, 12, 10, LEAF4_CACHE_PART, NA, 0 ) \
FIELD( 4, 0, EBX, 22, 10, LEAF4_CACHE_WAYS, NA, 0 ) \
FIELD( 4, 0, ECX, 0, 32, LEAF4_CACHE_SETS, NA, 0 ) \
FLAG( 4, 0, EDX, 0, 1, LEAF4_CACHE_WBINVD_NOT_GUARANTEED, NA, 0 ) \
FLAG( 4, 0, EDX, 1, 1, LEAF4_CACHE_IS_INCLUSIVE, NA, 0 ) \
FLAG( 4, 0, EDX, 2, 1, LEAF4_CACHE_COMPLEX_INDEXING, NA, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_5 \
FIELD( 5, 0, EAX, 0, 16, MWAIT_MIN_SIZE, NA, 0 ) \
FIELD( 5, 0, EBX, 0, 16, MWAIT_MAX_SIZE, NA, 0 ) \
FLAG( 5, 0, ECX, 0, 1, MWAIT_EXTENSIONS, NA, 0 ) \
FLAG( 5, 0, ECX, 1, 1, MWAIT_INTR_BREAK, NA, 0 ) \
FIELD( 5, 0, EDX, 0, 4, MWAIT_C0_SUBSTATE, NA, 0 ) \
FIELD( 5, 0, EDX, 4, 4, MWAIT_C1_SUBSTATE, NA, 0 ) \
FIELD( 5, 0, EDX, 8, 4, MWAIT_C2_SUBSTATE, NA, 0 ) \
FIELD( 5, 0, EDX, 12, 4, MWAIT_C3_SUBSTATE, NA, 0 ) \
FIELD( 5, 0, EDX, 16, 4, MWAIT_C4_SUBSTATE, NA, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_6 \
FLAG( 6, 0, EAX, 0, 1, THERMAL_SENSOR, NO, 0 ) \
FLAG( 6, 0, EAX, 1, 1, TURBO_MODE, NO, 0 ) \
FLAG( 6, 0, EAX, 2, 1, APIC_INVARIANT, ANY, 4 ) \
FLAG( 6, 0, EAX, 4, 1, PLN, NO, 0 ) \
FLAG( 6, 0, EAX, 5, 1, ECMD, NO, 0 ) \
FLAG( 6, 0, EAX, 6, 1, PTM, NO, 0 ) \
FLAG( 6, 0, EAX, 7, 1, HWP, NO, 0 ) \
FLAG( 6, 0, EAX, 8, 1, HWP_NOTIFICATION, NO, 0 ) \
FLAG( 6, 0, EAX, 9, 1, HWP_ACTIVITY_WINDOW, NO, 0 ) \
FLAG( 6, 0, EAX, 10, 1, HWP_ENERGY_PERFORMANCE_PREFERENCE, NO, 0 ) \
FLAG( 6, 0, EAX, 11, 1, HWP_PACKAGE_LEVEL_REQUEST, NO, 0 ) \
FLAG( 6, 0, EAX, 13, 1, HDC, NO, 0 ) \
FLAG( 6, 0, EAX, 14, 1, TURBO_BOOST_MAX_3, NO, 0 ) \
FLAG( 6, 0, EAX, 15, 1, HWP_CAPABILITIES, NO, 0 ) \
FLAG( 6, 0, EAX, 16, 1, HWP_PECI, NO, 0 ) \
FLAG( 6, 0, EAX, 17, 1, HWP_FLEXIBLE, NO, 0 ) \
FLAG( 6, 0, EAX, 18, 1, HWP_FAST_ACCESS, NO, 0 ) \
FLAG( 6, 0, EAX, 19, 1, HW_FEEDBACK, NO, 0 ) \
FLAG( 6, 0, EAX, 20, 1, HWP_IGNORE_IDLE_REQUEST, NO, 0 ) \
FLAG( 6, 0, EAX, 23, 1, HW_FEEDBACK_ENHANCED, NO, 0 ) \
FLAG( 6, 0, EAX, 24, 1, HWP_THERM_INTERRUPT_MSR, NO, 0 ) \
FIELD( 6, 0, EBX, 0, 4, NUM_INTR_THRESHOLDS, NO, 0 ) \
FLAG( 6, 0, ECX, 0, 1, HW_COORD_FEEDBACK, NO, 0 ) \
FLAG( 6, 0, ECX, 1, 1, ACNT2, ANY, 13 ) \
FLAG( 6, 0, ECX, 3, 1, ENERGY_PERF_BIAS, NO, 0 ) \
FIELD( 6, 0, ECX, 8, 4, HW_FEEDBACK_NUM_CLASSES, NO, 0 ) \
FLAG( 6, 0, EDX, 0, 1, PERF_CAP_REPORTING, NO, 0 ) \
FLAG( 6, 0, EDX, 1, 1, ENERGY_CAP_REPORTING, NO, 0 ) \
FIELD( 6, 0, EDX, 8, 4, HW_FEEDBACK_SIZE, NO, 0 ) \
FIELD( 6, 0, EDX, 16, 16, HW_FEEDBACK_INDEX, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_7 \
FIELD( 7, 0, EAX, 0, 32, LEAF_7_MAX_SUBLEVEL, YES, 18 ) \
FLAG( 7, 0, EBX, 0, 1, FSGSBASE, YES, 9 ) \
FLAG( 7, 0, EBX, 1, 1, TSC_ADJUST, ANY, 11 ) \
FLAG( 7, 0, EBX, 2, 1, SGX, ANY, 17 ) \
FLAG( 7, 0, EBX, 3, 1, BMI1, YES, 9 ) \
FLAG( 7, 0, EBX, 4, 1, HLE, ANY, 11 ) \
FLAG( 7, 0, EBX, 5, 1, AVX2, YES, 11 ) \
FLAG( 7, 0, EBX, 6, 1, FDP_EXCPTN_ONLY, ANY, 4 ) \
FLAG( 7, 0, EBX, 7, 1, SMEP, YES, 9 ) \
FLAG( 7, 0, EBX, 8, 1, BMI2, YES, 11 ) \
FLAG( 7, 0, EBX, 9, 1, ENFSTRG, YES, 9 ) \
FLAG( 7, 0, EBX, 10, 1, INVPCID, YES, 11 ) \
FLAG( 7, 0, EBX, 11, 1, RTM, YES, 11 ) \
FLAG( 7, 0, EBX, 12, 1, PQM, NO, 0 ) \
FLAG( 7, 0, EBX, 13, 1, FP_SEGMENT_ZERO, ANY, 11 ) \
FLAG( 7, 0, EBX, 14, 1, MPX, ANY, 13 ) \
FLAG( 7, 0, EBX, 15, 1, PQE, YES, 20 ) \
FLAG( 7, 0, EBX, 16, 1, AVX512F, YES, 13 ) \
FLAG( 7, 0, EBX, 17, 1, AVX512DQ, YES, 13 ) \
FLAG( 7, 0, EBX, 18, 1, RDSEED, YES, 11 ) \
FLAG( 7, 0, EBX, 19, 1, ADX, YES, 11 ) \
FLAG( 7, 0, EBX, 20, 1, SMAP, YES, 11 ) \
FLAG( 7, 0, EBX, 21, 1, AVX512IFMA, YES, 17 ) \
FLAG( 7, 0, EBX, 23, 1, CLFLUSHOPT, YES, 13 ) \
FLAG( 7, 0, EBX, 24, 1, CLWB, YES, 13 ) \
FLAG( 7, 0, EBX, 25, 1, PT, NO, 0 ) \
FLAG( 7, 0, EBX, 26, 1, AVX512PF, YES, 13 ) \
FLAG( 7, 0, EBX, 27, 1, AVX512ER, YES, 13 ) \
FLAG( 7, 0, EBX, 28, 1, AVX512CD, YES, 13 ) \
FLAG( 7, 0, EBX, 29, 1, SHA, YES, 14 ) \
FLAG( 7, 0, EBX, 30, 1, AVX512BW, YES, 13 ) \
FLAG( 7, 0, EBX, 31, 1, AVX512VL, YES, 13 ) \
FLAG( 7, 0, ECX, 0, 1, PREFETCHWT1, YES, 13 ) \
FLAG( 7, 0, ECX, 1, 1, AVX512VBMI, YES, 17 ) \
FLAG( 7, 0, ECX, 2, 1, UMIP, YES, 17 ) \
FLAG( 7, 0, ECX, 3, 1, PKU, YES, 13 ) \
FLAG( 7, 0, ECX, 4, 1, OSPKE, ANY, 13 ) \
FLAG( 7, 0, ECX, 5, 1, WAITPKG, YES, 21 ) \
FLAG( 7, 0, ECX, 6, 1, AVX512VBMI2, YES, 17 ) \
FLAG( 7, 0, ECX, 7, 1, CET_SS, YES, 20 ) \
FLAG( 7, 0, ECX, 8, 1, GFNI, YES, 17 ) \
FLAG( 7, 0, ECX, 9, 1, VAES, YES, 17 ) \
FLAG( 7, 0, ECX, 10, 1, VPCLMULQDQ, YES, 17 ) \
FLAG( 7, 0, ECX, 11, 1, AVX512VNNI, YES, 17 ) \
FLAG( 7, 0, ECX, 12, 1, AVX512BITALG, YES, 17 ) \
FLAG( 7, 0, ECX, 13, 1, TME_EN, NO, 0 ) \
FLAG( 7, 0, ECX, 14, 1, AVX512VPOPCNTDQ, YES, 16 ) \
FLAG( 7, 0, ECX, 16, 1, VA57, NO, 0 ) \
FIELD( 7, 0, ECX, 17, 5, MAWA, NO, 0 ) \
FLAG( 7, 0, ECX, 22, 1, RDPID, YES, 17 ) \
FLAG( 7, 0, ECX, 23, 1, KEY_LOCKER, NO, 0 ) \
FLAG( 7, 0, ECX, 24, 1, BUS_LOCK_DB, NO, 0 ) \
FLAG( 7, 0, ECX, 25, 1, CLDEMOTE, YES, 18 ) \
FLAG( 7, 0, ECX, 27, 1, MOVDIRI, YES, 18 ) \
FLAG( 7, 0, ECX, 28, 1, MOVDIR64B, YES, 18 ) \
FLAG( 7, 0, ECX, 29, 1, ENQCMD, YES, FUT ) \
FLAG( 7, 0, ECX, 30, 1, SGX_LC, ANY, 17 ) \
FLAG( 7, 0, ECX, 31, 1, PKS, YES, 20 ) \
FLAG( 7, 0, EDX, 1, 1, SGK_KEYS, NO, 0 ) \
FLAG( 7, 0, EDX, 2, 1, AVX512QVNNIW, YES, 16 ) \
FLAG( 7, 0, EDX, 3, 1, AVX512QFMAPS, YES, 16 ) \
FLAG( 7, 0, EDX, 4, 1, FAST_SHORT_REPMOV, YES, 18 ) \
FLAG( 7, 0, EDX, 5, 1, UINTR, NO, 0 ) \
FLAG( 7, 0, EDX, 8, 1, AVX512VP2INTERSECT, YES, 18 ) \
FLAG( 7, 0, EDX, 9, 1, SRBDS_CTRL, NO, 0 ) \
FLAG( 7, 0, EDX, 10, 1, MDCLEAR, YES, 9 ) \
FLAG( 7, 0, EDX, 11, 1, RTM_ALWAYS_ABORT, NO, 0 ) \
FLAG( 7, 0, EDX, 13, 1, RTM_FORCE_ABORT, NO, 0 ) \
FLAG( 7, 0, EDX, 14, 1, SERIALIZE, YES, 20 ) \
FLAG( 7, 0, EDX, 15, 1, HYBRID, NO, 0 ) \
FLAG( 7, 0, EDX, 16, 1, TSXLDTRK, YES, 21 ) \
FLAG( 7, 0, EDX, 18, 1, PCONFIG, NO, 0 ) \
FLAG( 7, 0, EDX, 19, 1, ARCH_LBR, YES, 20 ) \
FLAG( 7, 0, EDX, 20, 1, CET_IBT, YES, 20 ) \
FLAG( 7, 0, EDX, 22, 1, AMX_BF16, YES, 20 ) \
FLAG( 7, 0, EDX, 23, 1, AVX512FP16, YES, 20 ) \
FLAG( 7, 0, EDX, 24, 1, AMX_TILE, YES, 20 ) \
FLAG( 7, 0, EDX, 25, 1, AMX_INT8, YES, 20 ) \
FLAG( 7, 0, EDX, 26, 1, IBRSIBPB, ANY, 9 ) \
FLAG( 7, 0, EDX, 27, 1, STIBP, YES, 9 ) \
FLAG( 7, 0, EDX, 28, 1, FCMD, YES, 9 ) \
FLAG( 7, 0, EDX, 29, 1, ARCH_CAPABILITIES, ANY, 9 ) \
FLAG( 7, 0, EDX, 30, 1, CORE_CAPABILITIES, NO, 0 ) \
FLAG( 7, 0, EDX, 31, 1, SSBD, YES, 9 ) \
FLAG( 7, 1, EAX, 3, 1, RAO_INT, NO, 0 ) \
FLAG( 7, 1, EAX, 4, 1, AVX_VNNI, YES, 20 ) \
FLAG( 7, 1, EAX, 5, 1, AVX512BF16, YES, 18 ) \
FLAG( 7, 1, EAX, 6, 1, LASS, NO, 0 ) \
FLAG( 7, 1, EAX, 7, 1, CMPCCXADD, NO, 0 ) \
FLAG( 7, 1, EAX, 8, 1, ARCH_PERFMON_EXT, NO, 0 ) \
FLAG( 7, 1, EAX, 10, 1, FAST_ZERO_MOVSB, YES, 20 ) \
FLAG( 7, 1, EAX, 11, 1, FAST_SHORT_STOSB, YES, 20 ) \
FLAG( 7, 1, EAX, 12, 1, FAST_SHORT_CMPSB_SCASB, YES, 20 ) \
FLAG( 7, 1, EAX, 19, 1, WRMSRNS, NO, 0 ) \
FLAG( 7, 1, EAX, 21, 1, AMX_FP16, YES, 21 ) \
FLAG( 7, 1, EAX, 22, 1, HRESET, NO, 0 ) \
FLAG( 7, 1, EAX, 23, 1, AVX_IFMA, YES, FUT ) \
FLAG( 7, 1, EAX, 26, 1, LAM, NO, 0 ) \
FLAG( 7, 1, EAX, 27, 1, MSRLIST, NO, 0 ) \
FLAG( 7, 1, EBX, 0, 1, LEAF7_PPIN, NO, 0 ) \
FLAG( 7, 1, EDX, 4, 1, AVX_VNNI_INT8, YES, FUT ) \
FLAG( 7, 1, EDX, 5, 1, AVX_NE_CONVERT, NO, 0 ) \
FLAG( 7, 1, EDX, 8, 1, AMX_COMPLEX, NO, 0 ) \
FLAG( 7, 1, EDX, 14, 1, PREFETCHI, YES, 21 ) \
FLAG( 7, 1, EDX, 18, 1, CET_SSS, NO, 0 ) \
FLAG( 7, 2, EDX, 0, 1, PSFD, YES, 20 ) \
FLAG( 7, 2, EDX, 1, 1, IPRED_CTRL, YES, 21 ) \
FLAG( 7, 2, EDX, 2, 1, RRSBA_CTRL, YES, 21 ) \
FLAG( 7, 2, EDX, 3, 1, DDPD_U, YES, 21 ) \
FLAG( 7, 2, EDX, 4, 1, BHI_CTRL, YES, 21 ) \
FLAG( 7, 2, EDX, 5, 1, MCDT_NO, NO, 0 ) \
FLAG( 7, 2, EDX, 6, 1, UC_LOCK_DISABLE, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_9 \
FIELD( 9, 0, EAX, 0, 32, IA32_PLATFORM_DCA_CAP_VAL, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_A \
FIELD( A, 0, EAX, 0, 8, PMC_VERSION, NA, 0 ) \
FIELD( A, 0, EAX, 8, 8, PMC_NUM_GEN, NA, 0 ) \
FIELD( A, 0, EAX, 16, 8, PMC_WIDTH_GEN, NA, 0 ) \
FIELD( A, 0, EAX, 24, 8, PMC_EBX_LENGTH, NA, 0 ) \
FLAG( A, 0, EBX, 0, 1, PMC_CORE_CYCLES, NA, 0 ) \
FLAG( A, 0, EBX, 1, 1, PMC_INSTR_RETIRED, NA, 0 ) \
FLAG( A, 0, EBX, 2, 1, PMC_REF_CYCLES, NA, 0 ) \
FLAG( A, 0, EBX, 3, 1, PMC_LAST_LVL_CREF, NA, 0 ) \
FLAG( A, 0, EBX, 4, 1, PMC_LAST_LVL_CMISS, NA, 0 ) \
FLAG( A, 0, EBX, 5, 1, PMC_BR_INST_RETIRED, NA, 0 ) \
FLAG( A, 0, EBX, 6, 1, PMC_BR_MISS_RETIRED, NA, 0 ) \
FLAG( A, 0, EBX, 7, 1, PMC_TOPDOWN_SLOTS, NA, 0 ) \
FLAG( A, 0, ECX, 0, 1, PMC_FIXED0, NA, 0 ) \
FLAG( A, 0, ECX, 1, 1, PMC_FIXED1, NA, 0 ) \
FLAG( A, 0, ECX, 2, 1, PMC_FIXED2, NA, 0 ) \
FLAG( A, 0, ECX, 3, 1, PMC_FIXED3, NA, 0 ) \
FIELD( A, 0, EDX, 0, 5, PMC_NUM_FIXED, NA, 0 ) \
FIELD( A, 0, EDX, 5, 8, PMC_WIDTH_FIXED, NA, 0 ) \
FLAG( A, 0, EDX, 15, 1, PMC_ANYTHREAD_DEPRECATED, NA, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_B \
FIELD( B, 0, EAX, 0, 5, TOPOLOGY_MASK_WIDTH, NA, 0 ) \
FIELD( B, 0, EBX, 0, 16, TOPOLOGY_CPUS_SHARING_LEVEL, NA, 0 ) \
FIELD( B, 0, ECX, 0, 8, TOPOLOGY_LEVEL_NUMBER, NA, 0 ) \
FIELD( B, 0, ECX, 8, 8, TOPOLOGY_LEVEL_TYPE, NA, 0 ) \
FIELD( B, 0, EDX, 0, 32, TOPOLOGY_X2APIC_ID, NA, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_D \
FLAG( D, 0, EAX, 0, 1, XCR0_MASTER_LEGACY_FP, YES, 8 ) \
FLAG( D, 0, EAX, 1, 1, XCR0_MASTER_SSE, YES, 8 ) \
FLAG( D, 0, EAX, 2, 1, XCR0_MASTER_YMM_H, YES, 8 ) \
FLAG( D, 0, EAX, 3, 1, XCR0_MASTER_BNDREGS, YES, 13 ) \
FLAG( D, 0, EAX, 4, 1, XCR0_MASTER_BNDCSR, YES, 13 ) \
FLAG( D, 0, EAX, 5, 1, XCR0_MASTER_OPMASK, YES, 13 ) \
FLAG( D, 0, EAX, 6, 1, XCR0_MASTER_ZMM_H, YES, 13 ) \
FLAG( D, 0, EAX, 7, 1, XCR0_MASTER_HI16_ZMM, YES, 13 ) \
FLAG( D, 0, EAX, 9, 1, XCR0_MASTER_PKRU, YES, 13 ) \
FLAG( D, 0, EAX, 17, 1, XCR0_MASTER_XTILECFG, YES, 20 ) \
FLAG( D, 0, EAX, 18, 1, XCR0_MASTER_XTILEDATA, YES, 20 ) \
FIELD( D, 0, EBX, 0, 32, XSAVE_ENABLED_SIZE, ANY, 8 ) \
FIELD( D, 0, ECX, 0, 32, XSAVE_MAX_SIZE, YES, 8 ) \
FIELD( D, 0, EDX, 0, 29, XCR0_MASTER_UPPER, NO, 0 ) \
FLAG( D, 0, EDX, 30, 1, XCR0_MASTER_LWP, NO, 0 ) \
FLAG( D, 0, EDX, 31, 1, XCR0_MASTER_EXTENDED_XSAVE, NO, 0 ) \
FLAG( D, 1, EAX, 0, 1, XSAVEOPT, YES, 11 ) \
FLAG( D, 1, EAX, 1, 1, XSAVEC, YES, 13 ) \
FLAG( D, 1, EAX, 2, 1, XGETBV_ECX1, YES, 17 ) \
FLAG( D, 1, EAX, 3, 1, XSAVES, YES, 13 ) \
FLAG( D, 1, EAX, 4, 1, XFD, YES, 20 ) \
FIELD( D, 1, EBX, 0, 32, XSAVES_ENABLED_SIZE, ANY, 13 ) \
FLAG( D, 1, ECX, 8, 1, XSS_MASTER_PT, NO, 0 ) \
FLAG( D, 1, ECX, 10, 1, XSS_MASTER_PASID, YES, FUT ) \
FLAG( D, 1, ECX, 11, 1, XSS_MASTER_CET_U, YES, 20 ) \
FLAG( D, 1, ECX, 12, 1, XSS_MASTER_CET_S, YES, 20 ) \
FLAG( D, 1, ECX, 13, 1, XSS_MASTER_HDC, NO, 0 ) \
FLAG( D, 1, ECX, 14, 1, XSS_MASTER_UINTR, NO, 0 ) \
FLAG( D, 1, ECX, 15, 1, XSS_MASTER_LBR, NO, 0 ) \
FLAG( D, 1, ECX, 16, 1, XSS_MASTER_HWP, NO, 0 ) \
FIELD( D, 1, EDX, 0, 32, XSS_MASTER_UPPER, NO, 0 ) \
FIELD( D, 2, EAX, 0, 32, XSAVE_YMM_SIZE, YES, 8 ) \
FIELD( D, 2, EBX, 0, 32, XSAVE_YMM_OFFSET, YES, 8 ) \
FLAG( D, 2, ECX, 0, 1, XSAVE_YMM_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 2, ECX, 1, 1, XSAVE_YMM_ALIGN, YES, 13 ) \
FLAG( D, 2, ECX, 2, 1, XSAVE_YMM_XFD, NO, 0 ) \
FIELD( D, 3, EAX, 0, 32, XSAVE_BNDREGS_SIZE, YES, 13 ) \
FIELD( D, 3, EBX, 0, 32, XSAVE_BNDREGS_OFFSET, YES, 13 ) \
FLAG( D, 3, ECX, 0, 1, XSAVE_BNDREGS_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 3, ECX, 1, 1, XSAVE_BNDREGS_ALIGN, YES, 13 ) \
FLAG( D, 3, ECX, 2, 1, XSAVE_BNDREGS_XFD, NO, 0 ) \
FIELD( D, 4, EAX, 0, 32, XSAVE_BNDCSR_SIZE, YES, 13 ) \
FIELD( D, 4, EBX, 0, 32, XSAVE_BNDCSR_OFFSET, YES, 13 ) \
FLAG( D, 4, ECX, 0, 1, XSAVE_BNDCSR_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 4, ECX, 1, 1, XSAVE_BNDCSR_ALIGN, YES, 13 ) \
FLAG( D, 4, ECX, 2, 1, XSAVE_BNDCSR_XFD, NO, 0 ) \
FIELD( D, 5, EAX, 0, 32, XSAVE_OPMASK_SIZE, YES, 13 ) \
FIELD( D, 5, EBX, 0, 32, XSAVE_OPMASK_OFFSET, YES, 13 ) \
FLAG( D, 5, ECX, 0, 1, XSAVE_OPMASK_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 5, ECX, 1, 1, XSAVE_OPMASK_ALIGN, YES, 13 ) \
FLAG( D, 5, ECX, 2, 1, XSAVE_OPMASK_XFD, NO, 0 ) \
FIELD( D, 6, EAX, 0, 32, XSAVE_ZMM_H_SIZE, YES, 13 ) \
FIELD( D, 6, EBX, 0, 32, XSAVE_ZMM_H_OFFSET, YES, 13 ) \
FLAG( D, 6, ECX, 0, 1, XSAVE_ZMM_H_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 6, ECX, 1, 1, XSAVE_ZMM_H_ALIGN, YES, 13 ) \
FLAG( D, 6, ECX, 2, 1, XSAVE_ZMM_H_XFD, NO, 0 ) \
FIELD( D, 7, EAX, 0, 32, XSAVE_HI16_ZMM_SIZE, YES, 13 ) \
FIELD( D, 7, EBX, 0, 32, XSAVE_HI16_ZMM_OFFSET, YES, 13 ) \
FLAG( D, 7, ECX, 0, 1, XSAVE_HI16_ZMM_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 7, ECX, 1, 1, XSAVE_HI16_ZMM_ALIGN, YES, 13 ) \
FLAG( D, 7, ECX, 2, 1, XSAVE_HI16_ZMM_XFD, NO, 0 ) \
FIELD( D, 8, EAX, 0, 32, XSAVES_PT_STATE_SIZE, NO, 0 ) \
FLAG( D, 8, ECX, 0, 1, XSAVES_PT_STATE_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 8, ECX, 1, 1, XSAVES_PT_STATE_ALIGN, NO, 0 ) \
FLAG( D, 8, ECX, 2, 1, XSAVES_PT_STATE_XFD, NO, 0 ) \
FIELD( D, 9, EAX, 0, 32, XSAVE_PKRU_SIZE, YES, 13 ) \
FIELD( D, 9, EBX, 0, 32, XSAVE_PKRU_OFFSET, YES, 13 ) \
FLAG( D, 9, ECX, 0, 1, XSAVE_PKRU_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 9, ECX, 1, 1, XSAVE_PKRU_ALIGN, YES, 13 ) \
FLAG( D, 9, ECX, 2, 1, XSAVE_PKRU_XFD, NO, 0 ) \
FIELD( D, 10, EAX, 0, 32, XSAVES_PASID_STATE_SIZE, YES, FUT ) \
FLAG( D, 10, ECX, 0, 1, XSAVES_PASID_STATE_SUP_BY_XSS, YES, FUT ) \
FLAG( D, 10, ECX, 1, 1, XSAVES_PASID_STATE_ALIGN, YES, FUT ) \
FLAG( D, 10, ECX, 2, 1, XSAVES_PASID_STATE_XFD, YES, FUT ) \
FIELD( D, 11, EAX, 0, 32, XSAVES_CET_U_SIZE, YES, 20 ) \
FLAG( D, 11, ECX, 0, 1, XSAVES_CET_U_SUP_BY_XSS, YES, 20 ) \
FLAG( D, 11, ECX, 1, 1, XSAVES_CET_U_ALIGN, YES, 20 ) \
FLAG( D, 11, ECX, 2, 1, XSAVES_CET_U_XFD, YES, 20 ) \
FIELD( D, 12, EAX, 0, 32, XSAVES_CET_S_SIZE, YES, 20 ) \
FLAG( D, 12, ECX, 0, 1, XSAVES_CET_S_SUP_BY_XSS, YES, 20 ) \
FLAG( D, 12, ECX, 1, 1, XSAVES_CET_S_ALIGN, YES, 20 ) \
FLAG( D, 12, ECX, 2, 1, XSAVES_CET_S_XFD, YES, 20 ) \
FIELD( D, 13, EAX, 0, 32, XSAVES_HDT_SIZE, NO, 0 ) \
FLAG( D, 13, ECX, 0, 1, XSAVES_HDT_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 13, ECX, 1, 1, XSAVES_HDT_ALIGN, NO, 0 ) \
FLAG( D, 13, ECX, 2, 1, XSAVES_HDT_XFD, NO, 0 ) \
FIELD( D, 14, EAX, 0, 32, XSAVES_UINTR_SIZE, NO, 0 ) \
FLAG( D, 14, ECX, 0, 1, XSAVES_UINTR_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 14, ECX, 1, 1, XSAVES_UINTR_ALIGN, NO, 0 ) \
FLAG( D, 14, ECX, 2, 1, XSAVES_UINTR_XFD, NO, 0 ) \
FIELD( D, 15, EAX, 0, 32, XSAVES_LBR_SIZE, NO, 0 ) \
FLAG( D, 15, ECX, 0, 1, XSAVES_LBR_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 15, ECX, 1, 1, XSAVES_LBR_ALIGN, NO, 0 ) \
FLAG( D, 15, ECX, 2, 1, XSAVES_LBR_XFD, NO, 0 ) \
FIELD( D, 16, EAX, 0, 32, XSAVES_HWP_SIZE, NO, 0 ) \
FLAG( D, 16, ECX, 0, 1, XSAVES_HWP_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 16, ECX, 1, 1, XSAVES_HWP_ALIGN, NO, 0 ) \
FLAG( D, 16, ECX, 2, 1, XSAVES_HWP_XFD, NO, 0 ) \
FIELD( D, 17, EAX, 0, 32, XSAVE_XTILECFG_SIZE, YES, 20 ) \
FIELD( D, 17, EBX, 0, 32, XSAVE_XTILECFG_OFFSET, YES, 20 ) \
FLAG( D, 17, ECX, 0, 1, XSAVE_XTILECFG_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 17, ECX, 1, 1, XSAVE_XTILECFG_ALIGN, YES, 20 ) \
FLAG( D, 17, ECX, 2, 1, XSAVE_XTILECFG_XFD, YES, 20 ) \
FIELD( D, 18, EAX, 0, 32, XSAVE_XTILEDATA_SIZE, YES, 20 ) \
FIELD( D, 18, EBX, 0, 32, XSAVE_XTILEDATA_OFFSET, YES, 20 ) \
FLAG( D, 18, ECX, 0, 1, XSAVE_XTILEDATA_SUP_BY_XSS, NO, 0 ) \
FLAG( D, 18, ECX, 1, 1, XSAVE_XTILEDATA_ALIGN, YES, 20 ) \
FLAG( D, 18, ECX, 2, 1, XSAVE_XTILEDATA_XFD, YES, 20 ) \
/* D, 62: AMD LWP leaf on BD, PD, SR. Dropped in Zen. Never referenced. */
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_F \
FIELD( F, 0, EBX, 0, 32, PQM_MAX_RMID, NO, 0 ) \
FLAG( F, 0, EDX, 1, 1, PQM_CMT_SUPPORT, NO, 0 ) \
FIELD( F, 1, EBX, 0, 32, PQM_CMT_CONV, NO, 0 ) \
FIELD( F, 1, ECX, 0, 32, PQM_CMT_NUM_RMID, NO, 0 ) \
FLAG( F, 1, EDX, 0, 1, PQM_CMT_OCCUPANCY, NO, 0 ) \
FLAG( F, 1, EDX, 1, 1, PQM_MBM_TOTAL, NO, 0 ) \
FLAG( F, 1, EDX, 2, 1, PQM_MBM_LOCAL, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_10 \
FLAG( 10, 0, EBX, 1, 1, PQE_L3, YES, 20 ) \
FLAG( 10, 0, EBX, 2, 1, PQE_L2, NO, 0 ) \
FLAG( 10, 0, EBX, 3, 1, PQE_MBA, NO, 0 ) \
FIELD( 10, 1, EAX, 0, 5, PQE_L3_MASK_LENGTH, YES, 20 ) \
FIELD( 10, 1, EBX, 0, 32, PQE_L3_ISOLATION_UNIT_MAP, NO, 0 ) \
FLAG( 10, 1, ECX, 2, 1, PQE_L3_CDP, NO, 0 ) \
FIELD( 10, 1, EDX, 0, 16, PQE_L3_MAX_COS_NUMBER, YES, 20 ) \
FIELD( 10, 2, EAX, 0, 5, PQE_L2_MASK_LENGTH, NO, 0 ) \
FIELD( 10, 2, EBX, 0, 32, PQE_L2_ISOLATION_UNIT_MAP, NO, 0 ) \
FLAG( 10, 2, ECX, 2, 1, PQE_L2_CDP, NO, 0 ) \
FIELD( 10, 2, EDX, 0, 16, PQE_L2_MAX_COS_NUMBER, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_12 \
FLAG( 12, 0, EAX, 0, 1, SGX1, ANY, 17 ) \
FLAG( 12, 0, EAX, 1, 1, SGX2, ANY, 21 ) \
FLAG( 12, 0, EAX, 5, 1, SGX_OVERSUB_ENCLV, NO, 0 ) \
FLAG( 12, 0, EAX, 6, 1, SGX_OVERSUB_ENCLS, NO, 0 ) \
FLAG( 12, 0, EAX, 7, 1, SGX_EVERIFYREPORT2, NO, 0 ) \
FLAG( 12, 0, EAX, 10, 1, SGX_EUPDATESVN, NO, 0 ) \
FLAG( 12, 0, EBX, 0, 1, SGX_MISCSELECT_EXINFO, ANY, FUT ) \
FIELD( 12, 0, EBX, 1, 31, SGX_MISCSELECT_RSVD, NO, 0 ) \
FIELD( 12, 0, EDX, 0, 8, MAX_ENCLAVE_SIZE_NOT64, ANY, 17 ) \
FIELD( 12, 0, EDX, 8, 8, MAX_ENCLAVE_SIZE_64, ANY, 17 ) \
FIELD( 12, 1, EAX, 0, 32, SECS_ATTRIBUTES0, ANY, 17 ) \
FIELD( 12, 1, EBX, 0, 32, SECS_ATTRIBUTES1, ANY, 17 ) \
FIELD( 12, 1, ECX, 0, 32, SECS_ATTRIBUTES2, ANY, 17 ) \
FIELD( 12, 1, EDX, 0, 32, SECS_ATTRIBUTES3, ANY, 17 ) \
FIELD( 12, 2, EAX, 0, 4, EPC00_VALID, ANY, 17 ) \
FIELD( 12, 2, EAX, 12, 20, EPC00_BASE_LOW, ANY, 17 ) \
FIELD( 12, 2, EBX, 0, 20, EPC00_BASE_HIGH, ANY, 17 ) \
FIELD( 12, 2, ECX, 0, 4, EPC00_PROTECTED, ANY, 17 ) \
FIELD( 12, 2, ECX, 12, 20, EPC00_SIZE_LOW, ANY, 17 ) \
FIELD( 12, 2, EDX, 0, 20, EPC00_SIZE_HIGH, ANY, 17 ) \
FIELD( 12, 3, EAX, 0, 4, EPC01_VALID, NO, 0 ) \
FIELD( 12, 3, EAX, 12, 20, EPC01_BASE_LOW, NO, 0 ) \
FIELD( 12, 3, EBX, 0, 20, EPC01_BASE_HIGH, NO, 0 ) \
FIELD( 12, 3, ECX, 0, 4, EPC01_PROTECTED, NO, 0 ) \
FIELD( 12, 3, ECX, 12, 20, EPC01_SIZE_LOW, NO, 0 ) \
FIELD( 12, 3, EDX, 0, 20, EPC01_SIZE_HIGH, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_14 \
FIELD( 14, 0, EAX, 0, 32, PT_MAX_SUBLEAF, NO, 0 ) \
FLAG( 14, 0, EBX, 0, 1, PT_CR3_FILTER, NO, 0 ) \
FLAG( 14, 0, EBX, 1, 1, PT_CFG_PSB_CYC, NO, 0 ) \
FLAG( 14, 0, EBX, 2, 1, PT_IP_FILTER_PERSIST_MSR, NO, 0 ) \
FLAG( 14, 0, EBX, 3, 1, PT_MTC, NO, 0 ) \
FLAG( 14, 0, EBX, 4, 1, PT_PTWRITE, NO, 0 ) \
FLAG( 14, 0, EBX, 5, 1, PT_POWER_EVENT, NO, 0 ) \
FLAG( 14, 0, EBX, 6, 1, PT_PSB_PMI, NO, 0 ) \
FLAG( 14, 0, EBX, 7, 1, PT_EVENT_TRACE_ENABLE, NO, 0 ) \
FLAG( 14, 0, EBX, 8, 1, PT_TNT_DISABLE, NO, 0 ) \
FLAG( 14, 0, ECX, 0, 1, PT_TOPA, NO, 0 ) \
FLAG( 14, 0, ECX, 1, 1, PT_TOPA_MULTI, NO, 0 ) \
FLAG( 14, 0, ECX, 2, 1, PT_SRO, NO, 0 ) \
FLAG( 14, 0, ECX, 3, 1, PT_TRACE_TRANS, NO, 0 ) \
FLAG( 14, 0, ECX, 31, 1, PT_LIP, NO, 0 ) \
FIELD( 14, 1, EAX, 0, 3, PT_NUM_ADDR_RANGES, NO, 0 ) \
FIELD( 14, 1, EAX, 16, 16, PT_AVAIL_MTC_ENCS, NO, 0 ) \
FIELD( 14, 1, EBX, 0, 16, PT_AVAIL_CYC_THRESH_ENCS, NO, 0 ) \
FIELD( 14, 1, EBX, 16, 16, PT_AVAIL_PSB_FREQ_ENCS, NO, 0 ) \
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_15 \
FIELD( 15, 0, EAX, 0, 32, DENOM_TSC_TO_CORE_CRYSTAL_CLK, NO, 0 ) \
FIELD( 15, 0, EBX, 0, 32, NUMER_TSC_TO_CORE_CRYSTAL_CLK, NO, 0 ) \
FIELD( 15, 0, ECX, 0, 32, CORE_CRYSTAL_CLK_FREQ, NO, 0 ) \
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_16 \
FIELD( 16, 0, EAX, 0, 16, PROC_BASE_FREQ, NO, 0 ) \
FIELD( 16, 0, EBX, 0, 16, PROC_MIN_FREQ, NO, 0 ) \
FIELD( 16, 0, ECX, 0, 16, BUS_FREQ, NO, 0 ) \
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_17 \
FIELD( 17, 0, EAX, 0, 31, MAX_SOCID_INDEX, NO, 0 ) \
FIELD( 17, 0, EBX, 0, 16, SOC_VENDOR_ID, NO, 0 ) \
FIELD( 17, 0, EBX, 16, 1, SOC_INDUSTRY_STD, NO, 0 ) \
FIELD( 17, 0, ECX, 0, 31, SOC_PROJECT_ID, NO, 0 ) \
FIELD( 17, 0, EDX, 0, 31, SOC_STEPPING_ID, NO, 0 ) \
FIELD( 17, 1, EAX, 0, 32, SOC_VENDOR_BRAND_STRING_1_0, NO, 0 ) \
FIELD( 17, 1, EBX, 0, 32, SOC_VENDOR_BRAND_STRING_1_1, NO, 0 ) \
FIELD( 17, 1, ECX, 0, 32, SOC_VENDOR_BRAND_STRING_1_2, NO, 0 ) \
FIELD( 17, 1, EDX, 0, 32, SOC_VENDOR_BRAND_STRING_1_3, NO, 0 ) \
FIELD( 17, 2, EAX, 0, 32, SOC_VENDOR_BRAND_STRING_2_0, NO, 0 ) \
FIELD( 17, 2, EBX, 0, 32, SOC_VENDOR_BRAND_STRING_2_1, NO, 0 ) \
FIELD( 17, 2, ECX, 0, 32, SOC_VENDOR_BRAND_STRING_2_2, NO, 0 ) \
FIELD( 17, 2, EDX, 0, 32, SOC_VENDOR_BRAND_STRING_2_3, NO, 0 ) \
FIELD( 17, 3, EAX, 0, 32, SOC_VENDOR_BRAND_STRING_3_0, NO, 0 ) \
FIELD( 17, 3, EBX, 0, 32, SOC_VENDOR_BRAND_STRING_3_1, NO, 0 ) \
FIELD( 17, 3, ECX, 0, 32, SOC_VENDOR_BRAND_STRING_3_2, NO, 0 ) \
FIELD( 17, 3, EDX, 0, 32, SOC_VENDOR_BRAND_STRING_3_3, NO, 0 ) \
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_18 \
FIELD( 18, 0, EAX, 0, 32, TLB_INFO_MAX_SUBLEAF, NO, 0 ) \
FLAG( 18, 0, EBX, 0, 1, TLB_INFO_LEVEL_SIZE_4K, NO, 0 ) \
FLAG( 18, 0, EBX, 1, 1, TLB_INFO_LEVEL_SIZE_2M, NO, 0 ) \
FLAG( 18, 0, EBX, 2, 1, TLB_INFO_LEVEL_SIZE_4M, NO, 0 ) \
FLAG( 18, 0, EBX, 3, 1, TLB_INFO_LEVEL_SIZE_1G, NO, 0 ) \
FIELD( 18, 0, EBX, 8, 3, TLB_INFO_PARTITIONING, NO, 0 ) \
FIELD( 18, 0, EBX, 16, 16, TLB_INFO_NUM_WAYS, NO, 0 ) \
FIELD( 18, 0, ECX, 0, 32, TLB_INFO_NUM_SETS, NO, 0 ) \
FIELD( 18, 0, EDX, 0, 5, TLB_INFO_TYPE, NO, 0 ) \
FIELD( 18, 0, EDX, 5, 3, TLB_INFO_LEVEL, NO, 0 ) \
FLAG( 18, 0, EDX, 8, 1, TLB_INFO_FULLY_ASSOCIATIVE, NO, 0 ) \
FIELD( 18, 0, EDX, 14, 12, TLB_INFO_MAX_ADDRESSABLE_IDS, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_19 \
FLAG( 19, 0, EAX, 0, 1, KEY_LOCKER_CPL0_ONLY, NO, 0 ) \
FLAG( 19, 0, EAX, 1, 1, KEY_LOCKER_NO_ENCRYPT, NO, 0 ) \
FLAG( 19, 0, EAX, 2, 1, KEY_LOCKER_NO_DECRYPT, NO, 0 ) \
FLAG( 19, 0, EBX, 0, 1, AESKLE, NO, 0 ) \
FLAG( 19, 0, EBX, 2, 1, AESKLE_WIDE, NO, 0 ) \
FLAG( 19, 0, EBX, 4, 1, KEY_LOCKER_MSRS, NO, 0 ) \
FLAG( 19, 0, ECX, 0, 1, LOADWKEY_NOBACKUP, NO, 0 ) \
FLAG( 19, 0, ECX, 1, 1, KEY_LOCKER_KEY_SOURCE, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_1A \
FIELD( 1A, 0, EAX, 0, 24, NATIVE_MODEL_ID, NO, 0 ) \
FIELD( 1A, 0, EAX, 24, 8, CORE_TYPE, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_1B \
FIELD( 1B, 0, EAX, 0, 12, PCONFIG_SUBLEAF_TYPE, NO, 0 ) \
FIELD( 1B, 0, EBX, 0, 32, PCONFIG_TARGET_ID1, NO, 0 ) \
FIELD( 1B, 0, ECX, 0, 32, PCONFIG_TARGET_ID2, NO, 0 ) \
FIELD( 1B, 0, EDX, 0, 32, PCONFIG_TARGET_ID3, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_1C \
FIELD( 1C, 0, EAX, 0, 8, LBR_DEPTH, YES, 20 ) \
FLAG( 1C, 0, EAX, 30, 1, LBR_DEEP_CSTATE_RESET, YES, 20 ) \
FLAG( 1C, 0, EAX, 31, 1, LBR_IP_CONTAINS_LIP, YES, 20 ) \
FLAG( 1C, 0, EBX, 0, 1, LBR_CPL_FILTERING, YES, 20 ) \
FLAG( 1C, 0, EBX, 1, 1, LBR_BRANCH_FILTERING, YES, 20 ) \
FLAG( 1C, 0, EBX, 2, 1, LBR_CALL_STACK_MODE, YES, 20 ) \
FLAG( 1C, 0, ECX, 0, 1, LBR_MISPREDICT, YES, 20 ) \
FLAG( 1C, 0, ECX, 1, 1, LBR_TIMED_LBRS, YES, 20 ) \
FLAG( 1C, 0, ECX, 2, 1, LBR_BRANCH_TYPE, YES, 20 ) \
FLAG( 1C, 0, ECX, 16, 1, LBR_EVENT_LOGGING_PMC0, NO, 0 ) \
FLAG( 1C, 0, ECX, 17, 1, LBR_EVENT_LOGGING_PMC1, NO, 0 ) \
FLAG( 1C, 0, ECX, 18, 1, LBR_EVENT_LOGGING_PMC2, NO, 0 ) \
FLAG( 1C, 0, ECX, 19, 1, LBR_EVENT_LOGGING_PMC3, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_1D \
FIELD( 1D, 0, EAX, 0, 32, TILE_PALETTE_MAX, YES, 20 ) \
FIELD( 1D, 1, EAX, 0, 16, TILE_PALETTE1_TOTAL_BYTES, YES, 20 ) \
FIELD( 1D, 1, EAX, 16, 16, TILE_PALETTE1_BYTES_PER_TILE, YES, 20 ) \
FIELD( 1D, 1, EBX, 0, 16, TILE_PALETTE1_BYTES_PER_ROW, YES, 20 ) \
FIELD( 1D, 1, EBX, 16, 16, TILE_PALETTE1_NUM_REGS, YES, 20 ) \
FIELD( 1D, 1, ECX, 0, 16, TILE_PALETTE1_MAX_ROWS, YES, 20 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_1E \
FIELD( 1E, 0, EBX, 0, 8, TMUL_MAX_K, YES, 20 ) \
FIELD( 1E, 0, EBX, 8, 16, TMUL_MAX_N, YES, 20 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_1F \
FIELD( 1F, 0, EAX, 0, 5, TOPOLOGY_V2_MASK_WIDTH, NA, 0 ) \
FIELD( 1F, 0, EBX, 0, 16, TOPOLOGY_V2_CPUS_SHARING_LEVEL, NA, 0 ) \
FIELD( 1F, 0, ECX, 0, 8, TOPOLOGY_V2_LEVEL_NUMBER, NA, 0 ) \
FIELD( 1F, 0, ECX, 8, 8, TOPOLOGY_V2_LEVEL_TYPE, NA, 0 ) \
FIELD( 1F, 0, EDX, 0, 32, TOPOLOGY_V2_X2APIC_ID, NA, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_20 \
FIELD( 20, 0, EAX, 0, 32, HRESET_MAX_SUBLEAF, NO, 0 ) \
FIELD( 20, 0, EBX, 0, 32, HRESET_ENABLE_MSR_VALID_BITS, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_21 \
FIELD( 21, 0, EAX, 0, 32, TDX_MAX_SUBLEAF, NO, 0 ) \
FIELD( 21, 0, EBX, 0, 32, TDX_VENDOR1, NO, 0 ) \
FIELD( 21, 0, ECX, 0, 32, TDX_VENDOR3, NO, 0 ) \
FIELD( 21, 0, EDX, 0, 32, TDX_VENDOR2, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_23 \
FIELD( 23, 0, EAX, 0, 32, ARCH_PMC_MAX_SUBLEAF, NO, 0 ) \
FLAG( 23, 0, EBX, 0, 1, ARCH_PMC_UNITMASK2, NO, 0 ) \
FLAG( 23, 0, EBX, 1, 1, ARCH_PMC_ZBIT, NO, 0 ) \
FIELD( 23, 1, EAX, 0, 32, ARCH_PMC_GEN_BITMAP, NO, 0 ) \
FIELD( 23, 1, EBX, 0, 32, ARCH_PMC_FIXED_BITMAP, NO, 0 ) \
FLAG( 23, 3, EAX, 0, 1, ARCH_PMC_CORE_CYCLES, NO, 0 ) \
FLAG( 23, 3, EAX, 1, 1, ARCH_PMC_INSTR_RETIRED, NO, 0 ) \
FLAG( 23, 3, EAX, 2, 1, ARCH_PMC_REF_CYCLES, NO, 0 ) \
FLAG( 23, 3, EAX, 3, 1, ARCH_PMC_LAST_LVL_CREF, NO, 0 ) \
FLAG( 23, 3, EAX, 4, 1, ARCH_PMC_LAST_LVL_CMISS, NO, 0 ) \
FLAG( 23, 3, EAX, 5, 1, ARCH_PMC_BR_INST_RETIRED, NO, 0 ) \
FLAG( 23, 3, EAX, 6, 1, ARCH_PMC_BR_MISS_RETIRED, NO, 0 ) \
FLAG( 23, 3, EAX, 7, 1, ARCH_PMC_TOPDOWN_SLOTS, NO, 0 ) \
FLAG( 23, 3, EAX, 8, 1, ARCH_PMC_TOPDOWN_BACKEND, NO, 0 ) \
FLAG( 23, 3, EAX, 9, 1, ARCH_PMC_TOPDOWN_BAD_SPEC, NO, 0 ) \
FLAG( 23, 3, EAX, 10, 1, ARCH_PMC_TOPDOWN_FRONTEND, NO, 0 ) \
FLAG( 23, 3, EAX, 11, 1, ARCH_PMC_TOPDOWN_RETIRE, NO, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_400 \
FIELD(400, 0, EAX, 0, 32, MAX_HYP_LEVEL, NA, 0 ) \
FIELD(400, 0, EBX, 0, 32, HYPERVISOR_VENDOR0, NA, 0 ) \
FIELD(400, 0, ECX, 0, 32, HYPERVISOR_VENDOR1, NA, 0 ) \
FIELD(400, 0, EDX, 0, 32, HYPERVISOR_VENDOR2, NA, 0 )
/* LEVEL, SUB-LEVEL, REG, POS, SIZE, NAME, MON SUPP, HWV */
#define CPUID_FIELD_DATA_LEVEL_401 \
FIELD(401, 0, EAX, 0, 32, HV_INTERFACE_SIGNATURE, NA, 0 )