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v6pcieDMA.par
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v6pcieDMA.par
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Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
ubuntu:: Thu Oct 23 17:59:27 2014
par -w -intstyle ise -ol high -xe n -mt off v6pcieDMA_map.ncd v6pcieDMA.ncd
v6pcieDMA.pcf
Constraints file: v6pcieDMA.pcf.
Loading device for application Rf_Device from file '7a200t.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"v6pcieDMA" is an NCD, version 3.2, device xc7a200t, package fbg676, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
Device speed data version: "PRODUCTION 1.10 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 10,766 out of 269,200 3%
Number used as Flip Flops: 10,764
Number used as Latches: 2
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 9,261 out of 134,600 6%
Number used as logic: 7,309 out of 134,600 5%
Number using O6 output only: 5,058
Number using O5 output only: 579
Number using O5 and O6: 1,672
Number used as ROM: 0
Number used as Memory: 1,164 out of 46,200 2%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 1,164
Number using O6 output only: 818
Number using O5 output only: 1
Number using O5 and O6: 345
Number used exclusively as route-thrus: 788
Number with same-slice register load: 743
Number with same-slice carry load: 45
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,976 out of 33,650 11%
Number of LUT Flip Flop pairs used: 12,231
Number with an unused Flip Flop: 3,367 out of 12,231 27%
Number with an unused LUT: 2,970 out of 12,231 24%
Number of fully used LUT-FF pairs: 5,894 out of 12,231 48%
Number of slice register sites lost
to control set restrictions: 0 out of 269,200 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 5 out of 400 1%
Number of LOCed IOBs: 5 out of 5 100%
Number of bonded IPADs: 10
Number of bonded OPADs: 8
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 87 out of 365 23%
Number using RAMB36E1 only: 86
Number using FIFO36E1 only: 1
Number of RAMB18E1/FIFO18E1s: 1 out of 730 1%
Number using RAMB18E1 only: 1
Number using FIFO18E1 only: 0
Number of BUFG/BUFGCTRLs: 7 out of 32 21%
Number used as BUFGs: 6
Number used as BUFGCTRLs: 1
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 500 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 500 0%
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 500 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 40 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 40 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHCEs: 0 out of 120 0%
Number of BUFRs: 0 out of 40 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 0 out of 740 0%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of GTPE2_CHANNELs: 4 out of 8 50%
Number of LOCed GTPE2_CHANNELs: 4 out of 4 100%
Number of IBUFDS_GTE2s: 1 out of 8 12%
Number of LOCed IBUFDS_GTE2s: 1 out of 1 100%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 10 0%
Number of IN_FIFOs: 0 out of 40 0%
Number of MMCME2_ADVs: 1 out of 10 10%
Number of LOCed MMCME2_ADVs: 1 out of 1 100%
Number of OUT_FIFOs: 0 out of 40 0%
Number of PCIE_2_1s: 1 out of 1 100%
Number of LOCed PCIE_2_1s: 1 out of 1 100%
Number of PHASER_REFs: 0 out of 10 0%
Number of PHY_CONTROLs: 0 out of 10 0%
Number of PLLE2_ADVs: 0 out of 10 0%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 30 secs
Finished initial Timing Analysis. REAL time: 30 secs
WARNING:Par:288 - The signal trn_reset_n has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_do<59> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_txsyncdone<3> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_rxsyncdone<3> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_do<43> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_txsyncdone<2> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_rxsyncdone<2> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_do<27> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_txsyncdone<1> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_rxsyncdone<1> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_do<11> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_txsyncdone<0> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/gt_rxsyncdone<0> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/user_rxcdrlock<3> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/user_rxcdrlock<2> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/user_rxcdrlock<1> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/user_rxcdrlock<0> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/rxdlysresetdone<0> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/gt_top_i/pipe_wrapper_i/rxphaligndone_s<0> has no load. PAR will not attempt to
route this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/pcie_top_i/pcie_7x_i/mim_rx_raddr<12> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/pcie_top_i/pcie_7x_i/mim_rx_raddr<11> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/pcie_top_i/pcie_7x_i/mim_rx_waddr<12> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/pcie_top_i/pcie_7x_i/mim_rx_waddr<11> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/pcie_top_i/pcie_7x_i/mim_tx_raddr<12> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/pcie_top_i/pcie_7x_i/mim_tx_raddr<11> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/pcie_top_i/pcie_7x_i/mim_tx_waddr<12> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal make4Lanes.pcieCore/v7_pcie_i/pcie_top_i/pcie_7x_i/mim_tx_waddr<11> has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal ad9467_1/delay_rst_s has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<25> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<24> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<23> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<22> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<21> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<20> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<19> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<18> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<17> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<16> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<15> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<14> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<13> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<12> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<11> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<10> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<9> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<8> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<7> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<6> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<5> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<4> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<3> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Downstream_DMA_Engine/dsDMA_PA_Loaded<2> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<25> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<24> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<23> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<22> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<21> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<20> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<19> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<18> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<17> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal theTlpControl/rx_Itf/Upstream_DMA_Engine/usDMA_PA_Loaded<16> has no load. PAR will not attempt to route this
signal.
Starting Router
Phase 1 : 71579 unrouted; REAL time: 35 secs
Phase 2 : 50967 unrouted; REAL time: 38 secs
Phase 3 : 15190 unrouted; REAL time: 1 mins 42 secs
Phase 4 : 15192 unrouted; (Setup:71, Hold:20895, Component Switching Limit:0) REAL time: 1 mins 51 secs
Updating file: v6pcieDMA.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:76, Hold:19322, Component Switching Limit:0) REAL time: 2 mins 44 secs
Phase 6 : 0 unrouted; (Setup:76, Hold:19322, Component Switching Limit:0) REAL time: 2 mins 48 secs
Phase 7 : 0 unrouted; (Setup:76, Hold:19322, Component Switching Limit:0) REAL time: 2 mins 48 secs
Phase 8 : 0 unrouted; (Setup:76, Hold:19322, Component Switching Limit:0) REAL time: 2 mins 48 secs
Phase 9 : 0 unrouted; (Setup:76, Hold:0, Component Switching Limit:0) REAL time: 2 mins 53 secs
Total REAL time to Router completion: 2 mins 53 secs
Total CPU time to Router completion: 2 mins 58 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| ila0_trig2<155> | BUFGCTRL_X0Y0| No | 1857 | 0.400 | 1.749 |
+---------------------+--------------+------+------+------------+-------------+
| fifowr_clk |BUFGCTRL_X0Y30| No | 172 | 0.318 | 1.752 |
+---------------------+--------------+------+------+------------+-------------+
| icon_control0<0> |BUFGCTRL_X0Y29| No | 213 | 0.209 | 1.570 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
| v7_pcie_i/pipe_clk | BUFGCTRL_X0Y1| No | 365 | 0.381 | 1.792 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
| v7_pcie_i/user_clk | BUFGCTRL_X0Y3| No | 49 | 0.104 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
|v7_pcie_i/gt_top_i/p | | | | | |
|ipe_wrapper_i/clk_dc | | | | | |
| lk | BUFGCTRL_X0Y2| No | 68 | 0.373 | 1.792 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
|v7_pcie_i/gt_top_i/p | | | | | |
|ipe_wrapper_i/pipe_c | | | | | |
|lock_int.pipe_clock_ | | | | | |
| i/refclk |BUFGCTRL_X0Y31| No | 1 | 0.000 | 1.520 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_c | Local| | 1 | 0.000 | 0.000 |
+---------------------+--------------+------+------+------------+-------------+
| ila0_trig0<45> | Local| | 2 | 0.000 | 0.742 |
+---------------------+--------------+------+------+------------+-------------+
| clk_200MHz | Local| | 648 | 9.310 | 11.526 |
+---------------------+--------------+------+------+------------+-------------+
| icon_control0<13> | Local| | 4 | 0.000 | 0.725 |
+---------------------+--------------+------+------+------------+-------------+
|U_icon_pro/U0/iUPDAT | | | | | |
| E_OUT | Local| | 1 | 0.000 | 0.775 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
|v7_pcie_i/gt_top_i/p | | | | | |
|ipe_wrapper_i/qpll_q | | | | | |
| plloutclk | Local| | 4 | 0.000 | 0.000 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
|v7_pcie_i/gt_top_i/p | | | | | |
|ipe_wrapper_i/user_o | | | | | |
| obclk<3> | Local| | 1 | 0.000 | 5.245 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
|v7_pcie_i/gt_top_i/p | | | | | |
|ipe_wrapper_i/user_o | | | | | |
| obclk<2> | Local| | 1 | 0.000 | 5.125 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
|v7_pcie_i/gt_top_i/p | | | | | |
|ipe_wrapper_i/user_o | | | | | |
| obclk<1> | Local| | 1 | 0.000 | 6.419 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
|v7_pcie_i/gt_top_i/p | | | | | |
|ipe_wrapper_i/user_o | | | | | |
| obclk<0> | Local| | 1 | 0.000 | 6.732 |
+---------------------+--------------+------+------+------------+-------------+
|make4Lanes.pcieCore/ | | | | | |
|v7_pcie_i/gt_top_i/p | | | | | |
|ipe_wrapper_i/pipe_c | | | | | |
|lock_int.pipe_clock_ | | | | | |
| i/mmcm_fb | Local| | 1 | 0.000 | 0.012 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 76 (Setup: 76, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Number of Timing Constraints that were not applied: 6
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_userclk_200MHz_n = PERIOD TIMEGRP "use | SETUP | -0.076ns| 5.076ns| 1| 76
rclk_200MHz_n" 200 MHz HIGH 50% | HOLD | 0.007ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_ | MINPERIOD | 0.000ns| 4.000ns| 0| 0
SYSCLK * 2.5 HIGH 50% PRIORITY 2 | | | | |
----------------------------------------------------------------------------------------------------------
TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_ | SETUP | 0.028ns| 7.972ns| 0| 0
SYSCLK * 1.25 HIGH 50% PRIORITY 1 | HOLD | 0.041ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Pin to Pin Skew Constraint | MAXDELAY | 0.042ns| 0.560ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_CLK_USERCLK2 = PERIOD TIMEGRP "CLK_USE | SETUP | 0.118ns| 7.882ns| 0| 0
RCLK2" TS_SYSCLK * 1.25 HIGH 50% | HOLD | 0.118ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_adc_clk_in_n = PERIOD TIMEGRP "adc_clk | SETUP | 2.088ns| 7.912ns| 0| 0
_in_n" 100 MHz HIGH 50% | HOLD | 0.000ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_userclk_200MHz_p = PERIOD TIMEGRP "use | MINPERIOD | 2.830ns| 2.170ns| 0| 0
rclk_200MHz_p" 200 MHz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_CLK_USERCLK = PERIOD TIMEGRP "CLK_USER | SETUP | 4.406ns| 3.594ns| 0| 0
CLK" TS_SYSCLK * 1.25 HIGH 50% | HOLD | 0.113ns| | 0| 0
| MINPERIOD | 4.000ns| 4.000ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_adc_clk_in_p = PERIOD TIMEGRP "adc_clk | MINPERIOD | 7.830ns| 2.170ns| 0| 0
_in_p" 100 MHz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_SYSCLK = PERIOD TIMEGRP "SYSCLK" 100 M | MINPERIOD | 8.462ns| 1.538ns| 0| 0
Hz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_PIPE_RATE = MAXDELAY FROM TIMEGRP "MC_ | SETUP | 8.961ns| 7.039ns| 0| 0
PIPE" TS_CLK_USERCLK * 0.5 | HOLD | 0.172ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP | 12.494ns| 2.506ns| 0| 0
TO TIMEGRP "J_CLK" 15 ns | HOLD | 0.723ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP | 14.072ns| 0.928ns| 0| 0
TO TIMEGRP "U_CLK" 15 ns | HOLD | 0.263ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns H | SETUP | 18.463ns| 11.537ns| 0| 0
IGH 50% | HOLD | 0.142ns| | 0| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_J_TO_D_path" TIG | SETUP | N/A| 8.658ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_D_TO_J_path" TIG | SETUP | N/A| 3.202ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_J4_TO_D2_ila_pro_0_path" TIG | MAXDELAY | N/A| 4.585ns| N/A| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_J3_TO_D2_ila_pro_0_path" TIG | N/A | N/A| N/A| N/A| N/A
----------------------------------------------------------------------------------------------------------
PATH "TS_J2_TO_D2_ila_pro_0_path" TIG | N/A | N/A| N/A| N/A| N/A
----------------------------------------------------------------------------------------------------------
PATH "TS_D2_TO_T2_ila_pro_0_path" TIG | SETUP | N/A| 3.098ns| N/A| 0
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_SYSCLK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYSCLK | 10.000ns| 1.538ns| 10.000ns| 0| 0| 0| 83078|
| TS_CLK_125 | 8.000ns| 7.972ns| N/A| 0| 0| 7489| 0|
| TS_CLK_250 | 4.000ns| 4.000ns| N/A| 0| 0| 0| 0|
| TS_CLK_USERCLK | 8.000ns| 4.000ns| 3.520ns| 0| 0| 933| 726|
| TS_PIPE_RATE | 16.000ns| 7.039ns| N/A| 0| 0| 726| 0|
| TS_CLK_USERCLK2 | 8.000ns| 7.882ns| N/A| 0| 0| 73930| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 62 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 2 mins 56 secs
Total CPU time to PAR completion: 3 mins 1 secs
Peak Memory Usage: 1675 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 1 errors found.
Number of error messages: 0
Number of warning messages: 65
Number of info messages: 1
Writing design to file v6pcieDMA.ncd
PAR done!