Error in setup

[EnricoGiordano1992]

Hi wady101
I cannot build the project using the setup script. I am using PYNQ 2.5 (from tag) and Vivado 2019.1 .
This is the error:

ERROR: [BD 41-79] Exec TCL: Specified object '/adau1761_0' already exists. Please use a different name
ERROR: [BD 5-7] Error: running create_bd_cell  -vlnv xilinx.com:user:adau1761:1.0 -type ip -name adau1761_0 .
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv xilinx.com:user:adau1761:1.0 adau1761_0"
    (file "/media/mklab/TerabyteHD/PYNQ_Z2-Audio/addup.tcl" line 2)
INFO: [Common 17-17] undo 'startgroup'

    while executing
"source /media/mklab/TerabyteHD/PYNQ_Z2-Audio/addup.tcl"
    (procedure "create_root_design" line 442)
    invoked from within
"create_root_design """
    (file "base.tcl" line 4641)
INFO: [Common 17-206] Exiting Vivado at Wed Sep 30 21:03:33 2020...
makefile:13: recipe for target 'block_design' failed
make: *** [block_design] Error 1

This is the full log:

+ set -e
+ echo -ne '#                         (01%)\r'
+ echo -ne '##                        (08%)\r'
++ grep -E --line-number --with-filename save_bd_design ./PYNQ/boards/Pynq-Z2/base/base.tcl
++ cut -f2 -d:
++ head -1
+ x=4631
+ x=4628
+ sed -ie '4628 i source /media/mklab/TerabyteHD/PYNQ_Z2-Audio/addup.tcl' ./PYNQ/boards/Pynq-Z2/base/base.tcl
+ echo 'write_bd_tcl -force /media/mklab/TerabyteHD/PYNQ_Z2-Audio/base.tcl'
+ cp -r ./ip ./PYNQ/boards/ip/
+ pushd ./
/media/mklab/TerabyteHD/PYNQ_Z2-Audio /media/mklab/TerabyteHD/PYNQ_Z2-Audio
+ cd ./PYNQ/boards/Pynq-Z2/base/
+ make all
vivado -mode batch -source build_base_ip.tcl -notrace

****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

Sourcing tcl script '/home/mklab/.Xilinx/Vivado/Vivado_init.tcl'
0 Beta devices matching pattern found, 0 enabled.
source build_base_ip.tcl -notrace
Skipping building color_convert
Checking color_convert
Building pixel_pack IP
Checking pixel_pack
Building pixel_unpack IP
Checking pixel_unpack
Building trace_cntrl_32 IP
Checking trace_cntrl_32
Building trace_cntrl_64 IP
Checking trace_cntrl_64
HLS IP builds complete
INFO: [Common 17-206] Exiting Vivado at Wed Sep 30 21:02:48 2020...
vivado -mode batch -source base.tcl -notrace

****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

Sourcing tcl script '/home/mklab/.Xilinx/Vivado/Vivado_init.tcl'
0 Beta devices matching pattern found, 0 enabled.
source base.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/media/mklab/TerabyteHD/PYNQ_Z2-Audio/PYNQ/boards/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/media/mklab/TerabyteHD/XILINX/Vivado/2019.1/data/ip'.
INFO: [BD_TCL-3] Currently there is no design <base> in project, so creating one...
Wrote  : </media/mklab/TerabyteHD/PYNQ_Z2-Audio/PYNQ/boards/Pynq-Z2/base/base/base.srcs/sources_1/bd/base/base.bd> 
INFO: [BD_TCL-4] Making design <base> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "base".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog:  
xilinx.com:user:audio_codec_ctrl:1.0 xilinx.com:ip:axi_gpio:2.0 xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:xlconcat:2.1 xilinx.com:ip:xlconstant:1.1 xilinx.com:ip:xlslice:1.0 xilinx.com:ip:mdm:3.2 xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:user:interface_slice:1.0 xilinx.com:ip:axi_intc:4.1 xilinx.com:user:dff_en_reset_vector:1.0 xilinx.com:ip:axi_iic:2.0 xilinx.com:user:io_switch:1.1 xilinx.com:ip:microblaze:11.0 xilinx.com:ip:axi_bram_ctrl:4.1 xilinx.com:ip:axi_uartlite:2.0 xilinx.com:ip:xadc_wiz:3.3 xilinx.com:ip:axi_quad_spi:3.2 xilinx.com:ip:axi_timer:2.0 xilinx.com:ip:axi_dma:7.1 xilinx.com:ip:axis_data_fifo:2.0 xilinx.com:hls:trace_cntrl_64:1.4 xilinx.com:hls:trace_cntrl_32:1.4 xilinx.com:ip:axi_vdma:6.3 xilinx.com:user:wire_distributor:1.0 xilinx.com:user:mux_vector:1.0 xilinx.com:ip:lmb_v10:3.0 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:lmb_bram_if_cntlr:4.0 xilinx.com:ip:axis_register_slice:1.1 xilinx.com:hls:color_convert:1.0 xilinx.com:hls:pixel_pack:1.0 xilinx.com:hls:pixel_unpack:1.0 xilinx.com:user:color_swap:1.1 digilentinc.com:ip:dvi2rgb:1.7 xilinx.com:ip:v_vid_in_axi4s:4.0 xilinx.com:ip:v_tc:6.1 digilentinc.com:ip:axi_dynclk:1.0 digilentinc.com:ip:rgb2dvi:1.2 xilinx.com:ip:v_axi4s_vid_out:4.0  .
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_0: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide.
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_0: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide.
INFO: [Device 21-403] Loading part xc7z020clg400-1
WARNING: [BD 41-1306] The connection to interface pin /iop_arduino/intr/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_arduino/clk_100M(clk) and /iop_arduino/dff_en_reset_vector_0/clk(undef)
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_1: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide.
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_1: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide.
WARNING: [BD 41-1306] The connection to interface pin /iop_pmoda/intr/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmoda/clk_100M(clk) and /iop_pmoda/dff_en_reset_vector_0/clk(undef)
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_2: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide.
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_2: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide.
WARNING: [BD 41-1306] The connection to interface pin /iop_pmodb/intr/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmodb/clk_100M(clk) and /iop_pmodb/dff_en_reset_vector_0/clk(undef)
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_3: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide.
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_3: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide.
WARNING: [BD 41-1306] The connection to interface pin /iop_rpi/intr/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_rpi/clk_100M(clk) and /iop_rpi/dff_en_reset_vector_0/clk(undef)
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. 
WARNING: [BD 41-1306] The connection to interface pin /trace_analyzer_pi/trace_cntrl_64_0/trace_64_TDATA is being overridden by the user. This pin will not be connected as a part of interface connection trace_64
WARNING: [BD 41-1306] The connection to interface pin /trace_analyzer_pi/trace_cntrl_64_0/trace_64_TVALID is being overridden by the user. This pin will not be connected as a part of interface connection trace_64
WARNING: [BD 41-1306] The connection to interface pin /trace_analyzer_pi/trace_cntrl_64_0/trace_64_TKEEP is being overridden by the user. This pin will not be connected as a part of interface connection trace_64
WARNING: [BD 41-1306] The connection to interface pin /trace_analyzer_pi/trace_cntrl_64_0/trace_64_TSTRB is being overridden by the user. This pin will not be connected as a part of interface connection trace_64
WARNING: [BD 41-1306] The connection to interface pin /trace_analyzer_pmodb/trace_cntrl_32_0/trace_32_TDATA is being overridden by the user. This pin will not be connected as a part of interface connection trace_32
WARNING: [BD 41-1306] The connection to interface pin /trace_analyzer_pmodb/trace_cntrl_32_0/trace_32_TVALID is being overridden by the user. This pin will not be connected as a part of interface connection trace_32
WARNING: [BD 41-1306] The connection to interface pin /trace_analyzer_pmodb/trace_cntrl_32_0/trace_32_TKEEP is being overridden by the user. This pin will not be connected as a part of interface connection trace_32
WARNING: [BD 41-1306] The connection to interface pin /trace_analyzer_pmodb/trace_cntrl_32_0/trace_32_TSTRB is being overridden by the user. This pin will not be connected as a part of interface connection trace_32
WARNING: [BD 41-1306] The connection to interface pin /video/hdmi_in/frontend/axi_gpio_hdmiin/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1306] The connection to interface pin /video/hdmi_in/frontend/axi_gpio_hdmiin/gpio2_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO2
WARNING: [BD 41-1731] Type mismatch between connected pins: /video/hdmi_out/frontend/axi_dynclk/LOCKED_O(undef) and /video/hdmi_out/frontend/rgb2dvi_0/aRst_n(rst)
WARNING: [BD 41-1306] The connection to interface pin /video/hdmi_out/frontend/hdmi_out_hpd_video/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1306] The connection to interface pin /ps7_0/GPIO_O is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0
WARNING: [BD 41-1306] The connection to interface pin /system_interrupts/irq is being overridden by the user. This pin will not be connected as a part of interface connection interrupt
Slave segment </ps7_0/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into address space </axi_dma_0/Data_MM2S> at <0x0000_0000 [ 512M ]>
Slave segment </ps7_0/S_AXI_HP2/HP2_DDR_LOWOCM> is being mapped into address space </axi_dma_0/Data_S2MM> at <0x0000_0000 [ 512M ]>
Slave segment </adau1761_0/S_AXI/S_AXI_reg> is being mapped into address space </ps7_0/Data> at <0x43C0_0000 [ 64K ]>
Slave segment </axi_dma_0/S_AXI_LITE/Reg> is being mapped into address space </ps7_0/Data> at <0x4040_0000 [ 64K ]>
Slave segment </segment_stream_0/S_AXI/S_AXI_reg> is being mapped into address space </ps7_0/Data> at <0x83C0_0000 [ 64K ]>
ERROR: [BD 41-79] Exec TCL: Specified object '/adau1761_0' already exists. Please use a different name
ERROR: [BD 5-7] Error: running create_bd_cell  -vlnv xilinx.com:user:adau1761:1.0 -type ip -name adau1761_0 .
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv xilinx.com:user:adau1761:1.0 adau1761_0"
    (file "/media/mklab/TerabyteHD/PYNQ_Z2-Audio/addup.tcl" line 2)
INFO: [Common 17-17] undo 'startgroup'

    while executing
"source /media/mklab/TerabyteHD/PYNQ_Z2-Audio/addup.tcl"
    (procedure "create_root_design" line 442)
    invoked from within
"create_root_design """
    (file "base.tcl" line 4641)
INFO: [Common 17-206] Exiting Vivado at Wed Sep 30 21:03:33 2020...
makefile:13: recipe for target 'block_design' failed
make: *** [block_design] Error 1

[wady101]

@EnricoGiordano1992 not actively maintaining this repo for recent versions for Vivado (was tested on 2018.1 and 2018.3) and PYNQ, but I don't mind helping!
From what I can see, the error message says the audio IP already exists in the IPI. If I remember correctly, I did not add any check for that IP - either way the two options you have are:
a) Restart Vivado and run it again (reclone and rerun the script)
b) Comment this line

PYNQ_Z2-Audio/sources/base.tcl

Line 3206 in fc95718

set adau1761_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:adau1761:1.0 adau1761_0 ]

as the error states that it can somehow find adau1761_0 which should not be the case.

Let me know the outcome 👍

[EnricoGiordano1992]

Ok good, if you agree, I can share the code for the latest support for PYNQ and tools!
the problem is solved, but...now I have another problem.
During the last make, I have this error:

arm-linux-gnueabihf-gcc -fPIC -I ../inc/  -I ../bsp/ps7_cortexa9_0/include/ -c -g3 -gstabs adau1762.cpp ../src/i2cps.c ../src/uio.c
arm-linux-gnueabihf-gcc: error: ../src/i2cps.c: No such file or directory
arm-linux-gnueabihf-gcc: error: ../src/uio.c: No such file or directory
Makefile:16: recipe for target 'all' failed

I see that in the makefile there are some includes that is not presents in repository (../inc and ../bsp/ps7_cortexa9_0/include), do you have any suggestions?

Thanks a lot!

[wady101]

@EnricoGiordano1992 Those are from the Xilinx ARM BSP libraries:

https://ohwr.org/project/evo/tree/69f5408fd24bcdba0710e4ef07a0e3ba6de7c609/boot/microzed/BSP/ps7_cortexa9_0/include
https://github.com/PeterOgden/PYNQ/blob/7c31c77569077e6bfb9a386cf594609c44a92434/pynq/lib/_pynq/_audio/i2cps.c
https://github.com/PeterOgden/PYNQ/blob/7c31c77569077e6bfb9a386cf594609c44a92434/pynq/lib/_pynq/_audio/uio.c
https://github.com/PeterOgden/PYNQ/blob/7c31c77569077e6bfb9a386cf594609c44a92434/pynq/lib/_pynq/_audio/uio.h
https://github.com/PeterOgden/PYNQ/blob/7c31c77569077e6bfb9a386cf594609c44a92434/pynq/lib/_pynq/_audio/i2cps.h

I will have to update this repo with the above mentioned files. But with these, it should work alright (hopefully!). Probably remove that inc/, I don't remember where that is from

[EnricoGiordano1992]

Ok, I have done little progress...in attachment the code
PYNQ_Z2-Audio.zip

(on setup.sh, just set board_ip variable with your board ip)

Now I have a problem on jupyter notebook at this part:

Do you have any suggestions? Sorry for take your time but I think that this project is very usefull for the community :-)

[wady101]

@EnricoGiordano1992 no it's alright - keep firing those questions away! It is always fun to look at your old written code ;)
I guess comment that line out, (Line 42 in audio.py). I think that I used that for testing the whole flow

[EnricoGiordano1992]

Ok, I have prepared the full patch in this archive:
PYNQ_Z2-Audio.zip
Thanks for suggestions!
According to your example on Jupyter Notebook, how can I get a continuous stream in a numpy array in order to elaborate the datas? I want to implement a filter on the mic data and I can't understand on your example how elaborate the input data (I see that you can record a n-seconds audio and play it, but I don't understand how I can record without cuts the mic and meanwhile elaborate the numpy array).

[wady101]

@EnricoGiordano1992 Thanks for the patch, I'll put it in a separate branch! I am also okay if you want to submit it as a merge request :)
The purpose behind this example was to create a streaming audio IP - for the microphone side too! Hence, that is why you might not be able to modify the buffer as a whole.
Other than diving into the code yourself, I suggest - in Line 455,

PYNQ_Z2-Audio/audio.py

Line 455 in 4aa7c09

self._libaudio.record(self.mmio.length, uint_buffer, self.sample_len, self.uio_index, self.iic_index)

Try adding your own C++ function call there
For a Python change you might have to wait a while, I do plan to look at it this weekend - is there any specific kind of filter you are looking at?

[EnricoGiordano1992]

Ok, maybe at the next step I will implement the filter :)
Now I have another problem: when I record the audio (line in or mic, I have the same behaviour), the np.array output has a strange numbers inside...when I play the array with playinit function I have no problem, but converting the numpy array to wav file I have a completely distorted audio. I have plotted the array and I have this graph:

and I save the wav file in this way:

I have implemented the record function in this way:

from audio import *
from pynq import Overlay

import numpy as np
import pynq.lib.dma
from pynq import Xlnk

import psutil
import asyncio
import time
from threading import Thread

base=Overlay("./sources/AXIS_audio.bit")
Audiobj=base.adau1761_0

Audiobj.select_line_in()
#Audiobj.select_microphone()
Audiobj.recordinit(60)

xlnk = Xlnk()

dma_send = base.axi_dma_0

seconds = 1
coeff = 1
buffer_size = int((seconds * 2 * 48000) / coeff)
arr_total = np.array(list())
cma_ar = xlnk.cma_array(shape = buffer_size, dtype = "uint32")

def get_stream(threadName, seconds, iterations):
    global arr_total
    iterations *= coeff
    arr_total = np.array(list())
    while iterations > 0:
        base.segment_stream_0.write(0, buffer_size)

        dma_send.recvchannel.transfer(cma_ar)
        dma_send.recvchannel.wait()
        arr_total = np.concatenate((arr_total, cma_ar), axis=None)
        print(threadName + ": " + str(arr_total.shape))
        iterations -= 1

what is wrong in my code? Do you have any example about saving the numpy array output to a file? Thanks a lot!

[EnricoGiordano1992]

Ok, I think that the problem is that I have a PDM audio signal and not a PCM audio signal...do you have any suggestion for PDM -> PCM conversion? Thanks!

[EnricoGiordano1992]

Hi wady101
do you have any update?

[wady101]

@EnricoGiordano1992 , apologies for the late reply.
I am not sure if you have found the solution - but you would have to implement a LPF in Python right after you get the numpy array from the audio codec. https://en.wikipedia.org/wiki/Pulse-density_modulation#Digital-to-analog_conversion
You might have to use Scipy for this: https://docs.scipy.org/doc/scipy/reference/generated/scipy.signal.butter.html
An analog filter would be required to covert the output from the ADC back to the analog signal you are looking for. Is this what you were asking?

[EnricoGiordano1992]

Hi @wady101 , thanks for the support!
Unfortunately I didn't find any solutions... I tried to use a butterworth filter without success. Below the screenshot

I suppose that the problems are fs, lowcut and highcut parameters, because I obtain only noise. Do you have any working code or do you know what are the correct parameters? Thanks in advance!

[wady101]

Sadly no, @EnricoGiordano1992 .
But having a look at this - did you play around with fs ? Probably notch it up to 10k? Also did you take out the FFT and see the difference (before and after filter)?
Also go for a higher order - we aren't really looking at execution speed (for now):P
To clarify - do you want to hear the sound after the filter you applied or do you want to see visually?

[wady101]

One more thing which is the best test for this - is to play a sine wave on your phone and record it on the board.