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impl_vec_amd64.go
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impl_vec_amd64.go
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package compiler
import (
"errors"
"github.com/wasilibs/wazerox/internal/asm"
"github.com/wasilibs/wazerox/internal/asm/amd64"
"github.com/wasilibs/wazerox/internal/wazeroir"
)
// compileV128Const implements compiler.compileV128Const for amd64 architecture.
func (c *amd64Compiler) compileV128Const(o *wazeroir.UnionOperation) error {
if err := c.maybeCompileMoveTopConditionalToGeneralPurposeRegister(); err != nil {
return err
}
lo, hi := o.U1, o.U2
result, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
// We cannot directly load the value from memory to float regs,
// so we move it to int reg temporarily.
tmpReg, err := c.allocateRegister(registerTypeGeneralPurpose)
if err != nil {
return err
}
// Move the lower 64-bits.
if lo == 0 {
c.assembler.CompileRegisterToRegister(amd64.XORQ, tmpReg, tmpReg)
} else {
c.assembler.CompileConstToRegister(amd64.MOVQ, int64(lo), tmpReg)
}
c.assembler.CompileRegisterToRegister(amd64.MOVQ, tmpReg, result)
if lo != 0 && hi == 0 {
c.assembler.CompileRegisterToRegister(amd64.XORQ, tmpReg, tmpReg)
} else if hi != 0 {
c.assembler.CompileConstToRegister(amd64.MOVQ, int64(hi), tmpReg)
}
// Move the higher 64-bits with PINSRQ at the second element of 64x2 vector.
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, tmpReg, result, 1)
c.pushVectorRuntimeValueLocationOnRegister(result)
return nil
}
// compileV128Add implements compiler.compileV128Add for amd64 architecture.
func (c *amd64Compiler) compileV128Add(o *wazeroir.UnionOperation) error {
x2 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x2); err != nil {
return err
}
x1 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x1); err != nil {
return err
}
var inst asm.Instruction
shape := o.B1
switch shape {
case wazeroir.ShapeI8x16:
inst = amd64.PADDB
case wazeroir.ShapeI16x8:
inst = amd64.PADDW
case wazeroir.ShapeI32x4:
inst = amd64.PADDD
case wazeroir.ShapeI64x2:
inst = amd64.PADDQ
case wazeroir.ShapeF32x4:
inst = amd64.ADDPS
case wazeroir.ShapeF64x2:
inst = amd64.ADDPD
}
c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register)
c.pushVectorRuntimeValueLocationOnRegister(x1.register)
c.locationStack.markRegisterUnused(x2.register)
return nil
}
// compileV128Sub implements compiler.compileV128Sub for amd64 architecture.
func (c *amd64Compiler) compileV128Sub(o *wazeroir.UnionOperation) error {
x2 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x2); err != nil {
return err
}
x1 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x1); err != nil {
return err
}
var inst asm.Instruction
shape := o.B1
switch shape {
case wazeroir.ShapeI8x16:
inst = amd64.PSUBB
case wazeroir.ShapeI16x8:
inst = amd64.PSUBW
case wazeroir.ShapeI32x4:
inst = amd64.PSUBD
case wazeroir.ShapeI64x2:
inst = amd64.PSUBQ
case wazeroir.ShapeF32x4:
inst = amd64.SUBPS
case wazeroir.ShapeF64x2:
inst = amd64.SUBPD
}
c.assembler.CompileRegisterToRegister(inst, x2.register, x1.register)
c.pushVectorRuntimeValueLocationOnRegister(x1.register)
c.locationStack.markRegisterUnused(x2.register)
return nil
}
// compileV128Load implements compiler.compileV128Load for amd64 architecture.
func (c *amd64Compiler) compileV128Load(o *wazeroir.UnionOperation) error {
result, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
offset := uint32(o.U2)
loadType := wazeroir.V128LoadType(o.B1)
switch loadType {
case wazeroir.V128LoadType128:
err = c.compileV128LoadImpl(amd64.MOVDQU, offset, 16, result)
case wazeroir.V128LoadType8x8s:
err = c.compileV128LoadImpl(amd64.PMOVSXBW, offset, 8, result)
case wazeroir.V128LoadType8x8u:
err = c.compileV128LoadImpl(amd64.PMOVZXBW, offset, 8, result)
case wazeroir.V128LoadType16x4s:
err = c.compileV128LoadImpl(amd64.PMOVSXWD, offset, 8, result)
case wazeroir.V128LoadType16x4u:
err = c.compileV128LoadImpl(amd64.PMOVZXWD, offset, 8, result)
case wazeroir.V128LoadType32x2s:
err = c.compileV128LoadImpl(amd64.PMOVSXDQ, offset, 8, result)
case wazeroir.V128LoadType32x2u:
err = c.compileV128LoadImpl(amd64.PMOVZXDQ, offset, 8, result)
case wazeroir.V128LoadType8Splat:
reg, err := c.compileMemoryAccessCeilSetup(offset, 1)
if err != nil {
return err
}
c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVBQZX, amd64ReservedRegisterForMemory, -1,
reg, 1, reg)
// pinsrb $0, reg, result
// pxor tmpVReg, tmpVReg
// pshufb tmpVReg, result
c.locationStack.markRegisterUsed(result)
tmpVReg, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRB, reg, result, 0)
c.assembler.CompileRegisterToRegister(amd64.PXOR, tmpVReg, tmpVReg)
c.assembler.CompileRegisterToRegister(amd64.PSHUFB, tmpVReg, result)
case wazeroir.V128LoadType16Splat:
reg, err := c.compileMemoryAccessCeilSetup(offset, 2)
if err != nil {
return err
}
c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVWQZX, amd64ReservedRegisterForMemory, -2,
reg, 1, reg)
// pinsrw $0, reg, result
// pinsrw $1, reg, result
// pshufd $0, result, result (result = result[0,0,0,0])
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, reg, result, 0)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, reg, result, 1)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0)
case wazeroir.V128LoadType32Splat:
reg, err := c.compileMemoryAccessCeilSetup(offset, 4)
if err != nil {
return err
}
c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVLQZX, amd64ReservedRegisterForMemory, -4,
reg, 1, reg)
// pinsrd $0, reg, result
// pshufd $0, result, result (result = result[0,0,0,0])
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRD, reg, result, 0)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0)
case wazeroir.V128LoadType64Splat:
reg, err := c.compileMemoryAccessCeilSetup(offset, 8)
if err != nil {
return err
}
c.assembler.CompileMemoryWithIndexToRegister(amd64.MOVQ, amd64ReservedRegisterForMemory, -8,
reg, 1, reg)
// pinsrq $0, reg, result
// pinsrq $1, reg, result
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, reg, result, 0)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, reg, result, 1)
case wazeroir.V128LoadType32zero:
err = c.compileV128LoadImpl(amd64.MOVL, offset, 4, result)
case wazeroir.V128LoadType64zero:
err = c.compileV128LoadImpl(amd64.MOVQ, offset, 8, result)
}
if err != nil {
return err
}
c.pushVectorRuntimeValueLocationOnRegister(result)
return nil
}
func (c *amd64Compiler) compileV128LoadImpl(inst asm.Instruction, offset uint32, targetSizeInBytes int64, dst asm.Register) error {
offsetReg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes)
if err != nil {
return err
}
c.assembler.CompileMemoryWithIndexToRegister(inst, amd64ReservedRegisterForMemory, -targetSizeInBytes,
offsetReg, 1, dst)
return nil
}
// compileV128LoadLane implements compiler.compileV128LoadLane for amd64.
func (c *amd64Compiler) compileV128LoadLane(o *wazeroir.UnionOperation) error {
targetVector := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(targetVector); err != nil {
return err
}
laneSize, laneIndex := o.B1, o.B2
offset := uint32(o.U2)
var insertInst asm.Instruction
switch laneSize {
case 8:
insertInst = amd64.PINSRB
case 16:
insertInst = amd64.PINSRW
case 32:
insertInst = amd64.PINSRD
case 64:
insertInst = amd64.PINSRQ
}
targetSizeInBytes := int64(laneSize / 8)
offsetReg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes)
if err != nil {
return err
}
c.assembler.CompileMemoryWithIndexAndArgToRegister(insertInst, amd64ReservedRegisterForMemory, -targetSizeInBytes,
offsetReg, 1, targetVector.register, laneIndex)
c.pushVectorRuntimeValueLocationOnRegister(targetVector.register)
return nil
}
// compileV128Store implements compiler.compileV128Store for amd64.
func (c *amd64Compiler) compileV128Store(o *wazeroir.UnionOperation) error {
val := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(val); err != nil {
return err
}
const targetSizeInBytes = 16
offset := uint32(o.U2)
offsetReg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes)
if err != nil {
return err
}
c.assembler.CompileRegisterToMemoryWithIndex(amd64.MOVDQU, val.register,
amd64ReservedRegisterForMemory, -targetSizeInBytes, offsetReg, 1)
c.locationStack.markRegisterUnused(val.register, offsetReg)
return nil
}
// compileV128StoreLane implements compiler.compileV128StoreLane for amd64.
func (c *amd64Compiler) compileV128StoreLane(o *wazeroir.UnionOperation) error {
var storeInst asm.Instruction
laneSize := o.B1
laneIndex := o.B2
offset := uint32(o.U2)
switch laneSize {
case 8:
storeInst = amd64.PEXTRB
case 16:
storeInst = amd64.PEXTRW
case 32:
storeInst = amd64.PEXTRD
case 64:
storeInst = amd64.PEXTRQ
}
val := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(val); err != nil {
return err
}
targetSizeInBytes := int64(laneSize / 8)
offsetReg, err := c.compileMemoryAccessCeilSetup(offset, targetSizeInBytes)
if err != nil {
return err
}
c.assembler.CompileRegisterToMemoryWithIndexAndArg(storeInst, val.register,
amd64ReservedRegisterForMemory, -targetSizeInBytes, offsetReg, 1, laneIndex)
c.locationStack.markRegisterUnused(val.register, offsetReg)
return nil
}
// compileV128ExtractLane implements compiler.compileV128ExtractLane for amd64.
func (c *amd64Compiler) compileV128ExtractLane(o *wazeroir.UnionOperation) error {
v := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(v); err != nil {
return err
}
vreg := v.register
shape := o.B1
laneIndex := o.B2
signed := o.B3
switch shape {
case wazeroir.ShapeI8x16:
result, err := c.allocateRegister(registerTypeGeneralPurpose)
if err != nil {
return err
}
c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRB, vreg, result, laneIndex)
if signed {
c.assembler.CompileRegisterToRegister(amd64.MOVBLSX, result, result)
} else {
c.assembler.CompileRegisterToRegister(amd64.MOVBLZX, result, result)
}
c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32)
c.locationStack.markRegisterUnused(vreg)
case wazeroir.ShapeI16x8:
result, err := c.allocateRegister(registerTypeGeneralPurpose)
if err != nil {
return err
}
c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRW, vreg, result, laneIndex)
if signed {
c.assembler.CompileRegisterToRegister(amd64.MOVWLSX, result, result)
} else {
c.assembler.CompileRegisterToRegister(amd64.MOVWLZX, result, result)
}
c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32)
c.locationStack.markRegisterUnused(vreg)
case wazeroir.ShapeI32x4:
result, err := c.allocateRegister(registerTypeGeneralPurpose)
if err != nil {
return err
}
c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRD, vreg, result, laneIndex)
c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32)
c.locationStack.markRegisterUnused(vreg)
case wazeroir.ShapeI64x2:
result, err := c.allocateRegister(registerTypeGeneralPurpose)
if err != nil {
return err
}
c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRQ, vreg, result, laneIndex)
c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI64)
c.locationStack.markRegisterUnused(vreg)
case wazeroir.ShapeF32x4:
if laneIndex != 0 {
c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, vreg, vreg, laneIndex)
}
c.pushRuntimeValueLocationOnRegister(vreg, runtimeValueTypeF32)
case wazeroir.ShapeF64x2:
if laneIndex != 0 {
// This case we can assume LaneIndex == 1.
// We have to modify the val.register as, for example:
// 0b11 0b10 0b01 0b00
// | | | |
// [x3, x2, x1, x0] -> [x0, x0, x3, x2]
// where val.register = [x3, x2, x1, x0] and each xN = 32bits.
// Then, we interpret the register as float64, therefore, the float64 value is obtained as [x3, x2].
arg := byte(0b00_00_11_10)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, vreg, vreg, arg)
}
c.pushRuntimeValueLocationOnRegister(vreg, runtimeValueTypeF64)
}
return nil
}
// compileV128ReplaceLane implements compiler.compileV128ReplaceLane for amd64.
func (c *amd64Compiler) compileV128ReplaceLane(o *wazeroir.UnionOperation) error {
origin := c.locationStack.pop()
if err := c.compileEnsureOnRegister(origin); err != nil {
return err
}
vector := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(vector); err != nil {
return err
}
shape := o.B1
laneIndex := o.B2
switch shape {
case wazeroir.ShapeI8x16:
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRB, origin.register, vector.register, laneIndex)
case wazeroir.ShapeI16x8:
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, origin.register, vector.register, laneIndex)
case wazeroir.ShapeI32x4:
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRD, origin.register, vector.register, laneIndex)
case wazeroir.ShapeI64x2:
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, origin.register, vector.register, laneIndex)
case wazeroir.ShapeF32x4:
c.assembler.CompileRegisterToRegisterWithArg(amd64.INSERTPS, origin.register, vector.register,
// In INSERTPS instruction, the destination index is encoded at 4 and 5 bits of the argument.
// See https://www.felixcloutier.com/x86/insertps
laneIndex<<4,
)
case wazeroir.ShapeF64x2:
if laneIndex == 0 {
c.assembler.CompileRegisterToRegister(amd64.MOVSD, origin.register, vector.register)
} else {
c.assembler.CompileRegisterToRegister(amd64.MOVLHPS, origin.register, vector.register)
}
}
c.pushVectorRuntimeValueLocationOnRegister(vector.register)
c.locationStack.markRegisterUnused(origin.register)
return nil
}
// compileV128Splat implements compiler.compileV128Splat for amd64.
func (c *amd64Compiler) compileV128Splat(o *wazeroir.UnionOperation) (err error) {
origin := c.locationStack.pop()
if err = c.compileEnsureOnRegister(origin); err != nil {
return
}
var result asm.Register
shape := o.B1
switch shape {
case wazeroir.ShapeI8x16:
result, err = c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
c.locationStack.markRegisterUsed(result)
tmp, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRB, origin.register, result, 0)
c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, tmp)
c.assembler.CompileRegisterToRegister(amd64.PSHUFB, tmp, result)
case wazeroir.ShapeI16x8:
result, err = c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
c.locationStack.markRegisterUsed(result)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, origin.register, result, 0)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRW, origin.register, result, 1)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0)
case wazeroir.ShapeI32x4:
result, err = c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
c.locationStack.markRegisterUsed(result)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRD, origin.register, result, 0)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0)
case wazeroir.ShapeI64x2:
result, err = c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
c.locationStack.markRegisterUsed(result)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, origin.register, result, 0)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, origin.register, result, 1)
case wazeroir.ShapeF32x4:
result = origin.register
c.assembler.CompileRegisterToRegisterWithArg(amd64.INSERTPS, origin.register, result, 0)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PSHUFD, result, result, 0)
case wazeroir.ShapeF64x2:
result = origin.register
c.assembler.CompileRegisterToRegister(amd64.MOVQ, origin.register, result)
c.assembler.CompileRegisterToRegister(amd64.MOVLHPS, origin.register, result)
}
c.locationStack.markRegisterUnused(origin.register)
c.pushVectorRuntimeValueLocationOnRegister(result)
return nil
}
// compileV128Shuffle implements compiler.compileV128Shuffle for amd64.
func (c *amd64Compiler) compileV128Shuffle(o *wazeroir.UnionOperation) error {
w := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(w); err != nil {
return err
}
v := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(v); err != nil {
return err
}
wr, vr := w.register, v.register
tmp, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
consts := [32]byte{}
lanes := o.Us
for i, unsignedLane := range lanes {
lane := byte(unsignedLane)
if lane < 16 {
consts[i+16] = 0x80
consts[i] = lane
} else {
consts[i+16] = lane - 16
consts[i] = 0x80
}
}
err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(consts[:16]), tmp)
if err != nil {
return err
}
c.assembler.CompileRegisterToRegister(amd64.PSHUFB, tmp, vr)
err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(consts[16:]), tmp)
if err != nil {
return err
}
c.assembler.CompileRegisterToRegister(amd64.PSHUFB, tmp, wr)
c.assembler.CompileRegisterToRegister(amd64.ORPS, vr, wr)
c.pushVectorRuntimeValueLocationOnRegister(wr)
c.locationStack.markRegisterUnused(vr)
return nil
}
var swizzleConst = [16]byte{
0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
}
// compileV128Swizzle implements compiler.compileV128Swizzle for amd64.
func (c *amd64Compiler) compileV128Swizzle(*wazeroir.UnionOperation) error {
index := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(index); err != nil {
return err
}
base := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(base); err != nil {
return err
}
idxReg, baseReg := index.register, base.register
tmp, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
err = c.assembler.CompileStaticConstToRegister(amd64.MOVDQU, asm.NewStaticConst(swizzleConst[:]), tmp)
if err != nil {
return err
}
c.assembler.CompileRegisterToRegister(amd64.PADDUSB, tmp, idxReg)
c.assembler.CompileRegisterToRegister(amd64.PSHUFB, idxReg, baseReg)
c.pushVectorRuntimeValueLocationOnRegister(baseReg)
c.locationStack.markRegisterUnused(idxReg)
return nil
}
// compileV128AnyTrue implements compiler.compileV128AnyTrue for amd64.
func (c *amd64Compiler) compileV128AnyTrue(*wazeroir.UnionOperation) error {
v := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(v); err != nil {
return err
}
vreg := v.register
c.assembler.CompileRegisterToRegister(amd64.PTEST, vreg, vreg)
c.locationStack.pushRuntimeValueLocationOnConditionalRegister(amd64.ConditionalRegisterStateNE)
c.locationStack.markRegisterUnused(vreg)
return nil
}
// compileV128AllTrue implements compiler.compileV128AllTrue for amd64.
func (c *amd64Compiler) compileV128AllTrue(o *wazeroir.UnionOperation) error {
v := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(v); err != nil {
return err
}
tmp, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
var cmpInst asm.Instruction
shape := o.B1
switch shape {
case wazeroir.ShapeI8x16:
cmpInst = amd64.PCMPEQB
case wazeroir.ShapeI16x8:
cmpInst = amd64.PCMPEQW
case wazeroir.ShapeI32x4:
cmpInst = amd64.PCMPEQD
case wazeroir.ShapeI64x2:
cmpInst = amd64.PCMPEQQ
}
c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, tmp)
c.assembler.CompileRegisterToRegister(cmpInst, v.register, tmp)
c.assembler.CompileRegisterToRegister(amd64.PTEST, tmp, tmp)
c.locationStack.markRegisterUnused(v.register, tmp)
c.locationStack.pushRuntimeValueLocationOnConditionalRegister(amd64.ConditionalRegisterStateE)
return nil
}
// compileV128BitMask implements compiler.compileV128BitMask for amd64.
func (c *amd64Compiler) compileV128BitMask(o *wazeroir.UnionOperation) error {
v := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(v); err != nil {
return err
}
result, err := c.allocateRegister(registerTypeGeneralPurpose)
if err != nil {
return err
}
shape := o.B1
switch shape {
case wazeroir.ShapeI8x16:
c.assembler.CompileRegisterToRegister(amd64.PMOVMSKB, v.register, result)
case wazeroir.ShapeI16x8:
// When we have:
// R1 = [R1(w1), R1(w2), R1(w3), R1(w4), R1(w5), R1(w6), R1(w7), R1(v8)]
// R2 = [R2(w1), R2(w2), R2(w3), R2(v4), R2(w5), R2(w6), R2(w7), R2(v8)]
// where RX(wn) is n-th signed word (16-bit) of RX register,
//
// "PACKSSWB R1, R2" produces
// R1 = [
// byte_sat(R1(w1)), byte_sat(R1(w2)), byte_sat(R1(w3)), byte_sat(R1(w4)),
// byte_sat(R1(w5)), byte_sat(R1(w6)), byte_sat(R1(w7)), byte_sat(R1(w8)),
// byte_sat(R2(w1)), byte_sat(R2(w2)), byte_sat(R2(w3)), byte_sat(R2(w4)),
// byte_sat(R2(w5)), byte_sat(R2(w6)), byte_sat(R2(w7)), byte_sat(R2(w8)),
// ]
// where R1 is the destination register, and
// byte_sat(w) = int8(w) if w fits as signed 8-bit,
// 0x80 if w is less than 0x80
// 0x7F if w is greater than 0x7f
//
// See https://www.felixcloutier.com/x86/packsswb:packssdw for detail.
//
// Therefore, v.register ends up having i-th and (i+8)-th bit set if i-th lane is negative (for i in 0..8).
c.assembler.CompileRegisterToRegister(amd64.PACKSSWB, v.register, v.register)
c.assembler.CompileRegisterToRegister(amd64.PMOVMSKB, v.register, result)
// Clear the higher bits than 8.
c.assembler.CompileConstToRegister(amd64.SHRQ, 8, result)
case wazeroir.ShapeI32x4:
c.assembler.CompileRegisterToRegister(amd64.MOVMSKPS, v.register, result)
case wazeroir.ShapeI64x2:
c.assembler.CompileRegisterToRegister(amd64.MOVMSKPD, v.register, result)
}
c.locationStack.markRegisterUnused(v.register)
c.pushRuntimeValueLocationOnRegister(result, runtimeValueTypeI32)
return nil
}
// compileV128And implements compiler.compileV128And for amd64.
func (c *amd64Compiler) compileV128And(*wazeroir.UnionOperation) error {
x2 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x2); err != nil {
return err
}
x1 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x1); err != nil {
return err
}
c.assembler.CompileRegisterToRegister(amd64.PAND, x2.register, x1.register)
c.locationStack.markRegisterUnused(x2.register)
c.pushVectorRuntimeValueLocationOnRegister(x1.register)
return nil
}
// compileV128Not implements compiler.compileV128Not for amd64.
func (c *amd64Compiler) compileV128Not(*wazeroir.UnionOperation) error {
v := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(v); err != nil {
return err
}
tmp, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
// Set all bits on tmp register.
c.assembler.CompileRegisterToRegister(amd64.PCMPEQD, tmp, tmp)
// Then XOR with tmp to reverse all bits on v.register.
c.assembler.CompileRegisterToRegister(amd64.PXOR, tmp, v.register)
c.pushVectorRuntimeValueLocationOnRegister(v.register)
return nil
}
// compileV128Or implements compiler.compileV128Or for amd64.
func (c *amd64Compiler) compileV128Or(*wazeroir.UnionOperation) error {
x2 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x2); err != nil {
return err
}
x1 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x1); err != nil {
return err
}
c.assembler.CompileRegisterToRegister(amd64.POR, x2.register, x1.register)
c.locationStack.markRegisterUnused(x2.register)
c.pushVectorRuntimeValueLocationOnRegister(x1.register)
return nil
}
// compileV128Xor implements compiler.compileV128Xor for amd64.
func (c *amd64Compiler) compileV128Xor(*wazeroir.UnionOperation) error {
x2 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x2); err != nil {
return err
}
x1 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x1); err != nil {
return err
}
c.assembler.CompileRegisterToRegister(amd64.PXOR, x2.register, x1.register)
c.locationStack.markRegisterUnused(x2.register)
c.pushVectorRuntimeValueLocationOnRegister(x1.register)
return nil
}
// compileV128Bitselect implements compiler.compileV128Bitselect for amd64.
func (c *amd64Compiler) compileV128Bitselect(*wazeroir.UnionOperation) error {
selector := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(selector); err != nil {
return err
}
x2 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x2); err != nil {
return err
}
x1 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x1); err != nil {
return err
}
// The following logic is equivalent to v128.or(v128.and(v1, selector), v128.and(v2, v128.not(selector)))
// See https://github.com/WebAssembly/spec/blob/wg-2.0.draft1/proposals/simd/SIMD.md#bitwise-select
c.assembler.CompileRegisterToRegister(amd64.PAND, selector.register, x1.register)
c.assembler.CompileRegisterToRegister(amd64.PANDN, x2.register, selector.register)
c.assembler.CompileRegisterToRegister(amd64.POR, selector.register, x1.register)
c.locationStack.markRegisterUnused(x2.register, selector.register)
c.pushVectorRuntimeValueLocationOnRegister(x1.register)
return nil
}
// compileV128AndNot implements compiler.compileV128AndNot for amd64.
func (c *amd64Compiler) compileV128AndNot(*wazeroir.UnionOperation) error {
x2 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x2); err != nil {
return err
}
x1 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x1); err != nil {
return err
}
c.assembler.CompileRegisterToRegister(amd64.PANDN, x1.register, x2.register)
c.locationStack.markRegisterUnused(x1.register)
c.pushVectorRuntimeValueLocationOnRegister(x2.register)
return nil
}
// compileV128Shr implements compiler.compileV128Shr for amd64.
func (c *amd64Compiler) compileV128Shr(o *wazeroir.UnionOperation) error {
// https://stackoverflow.com/questions/35002937/sse-simd-shift-with-one-byte-element-size-granularity
shape := o.B1
signed := o.B3
if shape == wazeroir.ShapeI8x16 {
return c.compileV128ShrI8x16Impl(signed)
} else if shape == wazeroir.ShapeI64x2 && signed {
return c.compileV128ShrI64x2SignedImpl()
} else {
return c.compileV128ShrImpl(o)
}
}
// compileV128ShrImpl implements shift right instructions except for i8x16 (logical/arithmetic) and i64x2 (arithmetic).
func (c *amd64Compiler) compileV128ShrImpl(o *wazeroir.UnionOperation) error {
s := c.locationStack.pop()
if err := c.compileEnsureOnRegister(s); err != nil {
return err
}
x1 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x1); err != nil {
return err
}
vecTmp, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
var moduleConst int64
var shift asm.Instruction
shape := o.B1
signed := o.B3
switch shape {
case wazeroir.ShapeI16x8:
moduleConst = 0xf // modulo 16.
if signed {
shift = amd64.PSRAW
} else {
shift = amd64.PSRLW
}
case wazeroir.ShapeI32x4:
moduleConst = 0x1f // modulo 32.
if signed {
shift = amd64.PSRAD
} else {
shift = amd64.PSRLD
}
case wazeroir.ShapeI64x2:
moduleConst = 0x3f // modulo 64.
shift = amd64.PSRLQ
}
gpShiftAmount := s.register
c.assembler.CompileConstToRegister(amd64.ANDQ, moduleConst, gpShiftAmount)
c.assembler.CompileRegisterToRegister(amd64.MOVL, gpShiftAmount, vecTmp)
c.assembler.CompileRegisterToRegister(shift, vecTmp, x1.register)
c.locationStack.markRegisterUnused(gpShiftAmount)
c.pushVectorRuntimeValueLocationOnRegister(x1.register)
return nil
}
// compileV128ShrI64x2SignedImpl implements compiler.compileV128Shr for i64x2 signed (arithmetic) shift.
// PSRAQ instruction requires AVX, so we emulate it without AVX instructions. https://www.felixcloutier.com/x86/psraw:psrad:psraq
func (c *amd64Compiler) compileV128ShrI64x2SignedImpl() error {
const shiftCountRegister = amd64.RegCX
s := c.locationStack.pop()
if s.register != shiftCountRegister {
// If another value lives on the CX register, we release it to the stack.
c.onValueReleaseRegisterToStack(shiftCountRegister)
if s.onStack() {
s.setRegister(shiftCountRegister)
c.compileLoadValueOnStackToRegister(s)
} else if s.onConditionalRegister() {
c.compileMoveConditionalToGeneralPurposeRegister(s, shiftCountRegister)
} else { // already on register.
old := s.register
c.assembler.CompileRegisterToRegister(amd64.MOVL, old, shiftCountRegister)
s.setRegister(shiftCountRegister)
c.locationStack.markRegisterUnused(old)
}
}
c.locationStack.markRegisterUsed(shiftCountRegister)
tmp, err := c.allocateRegister(registerTypeGeneralPurpose)
if err != nil {
return err
}
x1 := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(x1); err != nil {
return err
}
// Extract each lane into tmp, execute SHR on tmp, and write it back to the lane.
c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRQ, x1.register, tmp, 0)
c.assembler.CompileRegisterToRegister(amd64.SARQ, shiftCountRegister, tmp)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, tmp, x1.register, 0)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PEXTRQ, x1.register, tmp, 1)
c.assembler.CompileRegisterToRegister(amd64.SARQ, shiftCountRegister, tmp)
c.assembler.CompileRegisterToRegisterWithArg(amd64.PINSRQ, tmp, x1.register, 1)
c.locationStack.markRegisterUnused(shiftCountRegister)
c.pushVectorRuntimeValueLocationOnRegister(x1.register)
return nil
}
// i8x16LogicalSHRMaskTable is necessary for emulating non-existent packed bytes logical right shifts on amd64.
// The mask is applied after performing packed word shifts on the value to clear out the unnecessary bits.
var i8x16LogicalSHRMaskTable = [8 * 16]byte{ // (the number of possible shift amount 0, 1, ..., 7.) * 16 bytes.
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // for 0 shift
0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, // for 1 shift
0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, // for 2 shift
0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, // for 3 shift
0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, // for 4 shift
0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, // for 5 shift
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, // for 6 shift
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, // for 7 shift
}
// compileV128ShrI64x2SignedImpl implements compiler.compileV128Shr for i8x16 signed logical/arithmetic shifts.
// amd64 doesn't have packed byte shifts, so we need this special casing.
// See https://stackoverflow.com/questions/35002937/sse-simd-shift-with-one-byte-element-size-granularity
func (c *amd64Compiler) compileV128ShrI8x16Impl(signed bool) error {
s := c.locationStack.pop()
if err := c.compileEnsureOnRegister(s); err != nil {
return err
}
v := c.locationStack.popV128()
if err := c.compileEnsureOnRegister(v); err != nil {
return err
}
vecTmp, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
gpShiftAmount := s.register
c.assembler.CompileConstToRegister(amd64.ANDQ, 0x7, gpShiftAmount) // mod 8.
if signed {
c.locationStack.markRegisterUsed(vecTmp)
vecTmp2, err := c.allocateRegister(registerTypeVector)
if err != nil {
return err
}
vreg := v.register
// Copy the value from v.register to vecTmp.
c.assembler.CompileRegisterToRegister(amd64.MOVDQA, vreg, vecTmp)
// Assuming that we have
// vreg = [b1, ..., b16]
// vecTmp = [b1, ..., b16]
// at this point, then we use PUNPCKLBW and PUNPCKHBW to produce:
// vreg = [b1, b1, b2, b2, ..., b8, b8]
// vecTmp = [b9, b9, b10, b10, ..., b16, b16]
c.assembler.CompileRegisterToRegister(amd64.PUNPCKLBW, vreg, vreg)
c.assembler.CompileRegisterToRegister(amd64.PUNPCKHBW, vecTmp, vecTmp)
// Adding 8 to the shift amount, and then move the amount to vecTmp2.
c.assembler.CompileConstToRegister(amd64.ADDQ, 0x8, gpShiftAmount)
c.assembler.CompileRegisterToRegister(amd64.MOVL, gpShiftAmount, vecTmp2)
// Perform the word packed arithmetic right shifts on vreg and vecTmp.
// This changes these two registers as:
// vreg = [xxx, b1 >> s, xxx, b2 >> s, ..., xxx, b8 >> s]
// vecTmp = [xxx, b9 >> s, xxx, b10 >> s, ..., xxx, b16 >> s]
// where xxx is 1 or 0 depending on each byte's sign, and ">>" is the arithmetic shift on a byte.
c.assembler.CompileRegisterToRegister(amd64.PSRAW, vecTmp2, vreg)
c.assembler.CompileRegisterToRegister(amd64.PSRAW, vecTmp2, vecTmp)
// Finally, we can get the result by packing these two word vectors.
c.assembler.CompileRegisterToRegister(amd64.PACKSSWB, vecTmp, vreg)
c.locationStack.markRegisterUnused(gpShiftAmount, vecTmp)
c.pushVectorRuntimeValueLocationOnRegister(vreg)
} else {
c.assembler.CompileRegisterToRegister(amd64.MOVL, gpShiftAmount, vecTmp)
// amd64 doesn't have packed byte shifts, so we packed word shift here, and then mark-out
// the unnecessary bits below.
c.assembler.CompileRegisterToRegister(amd64.PSRLW, vecTmp, v.register)
gpTmp, err := c.allocateRegister(registerTypeGeneralPurpose)
if err != nil {
return err
}
// Read the initial address of the mask table into gpTmp register.
err = c.assembler.CompileStaticConstToRegister(amd64.LEAQ, asm.NewStaticConst(i8x16LogicalSHRMaskTable[:]), gpTmp)
if err != nil {