Support hierarchical instruction format

[wildlarva]

Is your feature request related to a problem? Please describe.
ARM instruction set is defined hierarchically. It is more readable to have a hierarchical instruction format in MC description when you define an ARM instruction format.

Describe the solution you'd like
Add instruction hierarchies to MC description specification like below:

instructions:
  - name: load_store_format_1
    format: xxxx:cond|010:op1|xxxxxxxxxxxxxxxxxxxx|x:op|xxxx
    sub_instructions:
      - name: store_register_format_3
        format: xxxx:cond|01|0:A|0x010:op1|xxxx:Rn|xxxxxxxxxxx|x:B|xxxx
        sub_instructions:
          - name: strt_1
            format: xxxx:cond|01|0|0|x:U|0|1|0|xxxx:Rn|xxxx:Rt|xxxxxxxxxxxx:imm12

Describe alternatives you've considered
N/A

Additional context
N/A