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TEDwingPro.ucf
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TEDwingPro.ucf
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##################################################################################
## Copyright 2013-2016 Istvan Hegedus
##
## FPGATED is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## FPGATED is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
##
##
## Contains assignment and iostandard information for Papilio TEDWing v1.x using Papilio Pro platform
##
##################################################################################
# Main Papilio Pro board wing pin [] to FPGA pin Pxx map
# -------C------- -------B------- -------A-------
# [GND] [C00] P114 [GND] [B00] P99 P100 [A15]
# [2V5] [C01] P115 [2V5] [B01] P97 P98 [A14]
# [3V3] [C02] P116 [3V3] [B02] P92 P93 [A13]
# [5V0] [C03] P117 [5V0] [B03] P87 P88 [A12]
# [C04] P118 [B04] P84 P85 [A11] [5V0]
# [C05] P119 [B05] P82 P83 [A10] [3V3]
# [C06] P120 [B06] P80 P81 [A09] [2V5]
# [C07] P121 [B07] P78 P79 [A08] [GND]
# [GND] [C08] P123 [GND] [B08] P74 P75 [A07]
# [2V5] [C09] P124 [2V5] [B09] P95 P67 [A06]
# [3V3] [C10] P126 [3V3] [B10] P62 P66 [A05]
# [5V0] [C11] P127 [5V0] [B11] P59 P61 [A04]
# [C12] P131 [B12] P57 P58 [A03] [5V0]
# [C13] P132 [B13] P55 P56 [A02] [3V3]
# [C14] P133 [B14] P50 P51 [A01] [2V5]
# [C15] P134 [B15] P47 P48 [A00] [GND]
## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
CONFIG PROHIBIT=P144;
CONFIG PROHIBIT=P69;
CONFIG PROHIBIT=P60;
# Crystal Clock - use 32MHz onboard oscillator
NET "CLK32" LOC = "P94" | IOSTANDARD = LVTTL | PERIOD = 31.25ns ;
# Wing1 Column A
#NET RGBS LOC = "P48" | IOSTANDARD = LVTTL;
#NET RS232_RX LOC = "P51" | IOSTANDARD = LVTTL;
#NET RS232_TX LOC = "P56" | IOSTANDARD = LVTTL;
NET RESET LOC = "P58" | IOSTANDARD = LVTTL;
NET AUDIO_R LOC = "P61" | IOSTANDARD = LVTTL;
NET AUDIO_L LOC = "P66" | IOSTANDARD = LVTTL;
#NET RAS LOC = "P67" | IOSTANDARD = LVTTL;
#NET RW LOC = "P75" | IOSTANDARD = LVTTL;
#NET CAS LOC = "P79" | IOSTANDARD = LVTTL;
NET IEC_DATAOUT LOC = "P81" | IOSTANDARD = LVTTL;
NET IEC_DATAIN LOC = "P83" | IOSTANDARD = LVTTL;
NET IEC_CLKOUT LOC = "P85" | IOSTANDARD = LVTTL;
NET IEC_CLKIN LOC = "P88" | IOSTANDARD = LVTTL;
NET IEC_ATNOUT LOC = "P93" | IOSTANDARD = LVTTL;
#NET IEC_ATNIN LOC = "P98" | IOSTANDARD = LVTTL;
NET IEC_RESET LOC = "P100" | IOSTANDARD = LVTTL;
# Wing1 Column B
#NET D[0] LOC = "P99" | IOSTANDARD = LVTTL;
#NET D[1] LOC = "P97" | IOSTANDARD = LVTTL;
#NET D[2] LOC = "P92" | IOSTANDARD = LVTTL;
#NET D[3] LOC = "P87" | IOSTANDARD = LVTTL;
#NET D[4] LOC = "P84" | IOSTANDARD = LVTTL;
#NET D[5] LOC = "P82" | IOSTANDARD = LVTTL;
#NET D[6] LOC = "P80" | IOSTANDARD = LVTTL;
#NET D[7] LOC = "P78" | IOSTANDARD = LVTTL;
#NET A[0] LOC = "P74" | IOSTANDARD = LVTTL;
#NET A[1] LOC = "P95" | IOSTANDARD = LVTTL;
#NET A[2] LOC = "P62" | IOSTANDARD = LVTTL;
#NET A[3] LOC = "P59" | IOSTANDARD = LVTTL;
#NET A[4] LOC = "P57" | IOSTANDARD = LVTTL;
#NET A[5] LOC = "P55" | IOSTANDARD = LVTTL;
#NET A[6] LOC = "P50" | IOSTANDARD = LVTTL;
#NET A[7] LOC = "P47" | IOSTANDARD = LVTTL;
# Wing2 Column C
NET VSYNC LOC = "P114" | IOSTANDARD = LVTTL;
NET HSYNC LOC = "P115" | IOSTANDARD = LVTTL;
NET RED[0] LOC = "P116" | IOSTANDARD = LVTTL;
NET RED[1] LOC = "P117" | IOSTANDARD = LVTTL;
NET RED[2] LOC = "P118" | IOSTANDARD = LVTTL;
NET RED[3] LOC = "P119" | IOSTANDARD = LVTTL;
NET GREEN[0] LOC = "P120" | IOSTANDARD = LVTTL;
NET GREEN[1] LOC = "P121" | IOSTANDARD = LVTTL;
NET GREEN[2] LOC = "P123" | IOSTANDARD = LVTTL;
NET GREEN[3] LOC = "P124" | IOSTANDARD = LVTTL;
NET BLUE[0] LOC = "P126" | IOSTANDARD = LVTTL;
NET BLUE[1] LOC = "P127" | IOSTANDARD = LVTTL;
NET BLUE[2] LOC = "P131" | IOSTANDARD = LVTTL;
NET BLUE[3] LOC = "P132" | IOSTANDARD = LVTTL;
NET PS2DAT LOC = "P133" | IOSTANDARD = LVTTL;
NET PS2CLK LOC = "P134" | IOSTANDARD = LVTTL;
# Papilo Pro non wing related pinouts
#RS232
#NET RX LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX
#NET TX LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX
# SDRAM related pins
NET SDRAM_ADDR(0) LOC="P140" | IOSTANDARD=LVTTL; # SDRAM_ADDR0
NET SDRAM_ADDR(1) LOC="P139" | IOSTANDARD=LVTTL; # SDRAM_ADDR1
NET SDRAM_ADDR(2) LOC="P138" | IOSTANDARD=LVTTL; # SDRAM_ADDR2
NET SDRAM_ADDR(3) LOC="P137" | IOSTANDARD=LVTTL; # SDRAM_ADDR3
NET SDRAM_ADDR(4) LOC="P46" | IOSTANDARD=LVTTL; # SDRAM_ADDR4
NET SDRAM_ADDR(5) LOC="P45" | IOSTANDARD=LVTTL; # SDRAM_ADDR5
NET SDRAM_ADDR(6) LOC="P44" | IOSTANDARD=LVTTL; # SDRAM_ADDR6
NET SDRAM_ADDR(7) LOC="P43" | IOSTANDARD=LVTTL; # SDRAM_ADDR7
NET SDRAM_ADDR(8) LOC="P41" | IOSTANDARD=LVTTL; # SDRAM_ADDR8
NET SDRAM_ADDR(9) LOC="P40" | IOSTANDARD=LVTTL; # SDRAM_ADDR9
NET SDRAM_ADDR(10) LOC="P141" | IOSTANDARD=LVTTL; # SDRAM_ADDR10
NET SDRAM_ADDR(11) LOC="P35" | IOSTANDARD=LVTTL; # SDRAM_ADDR11
#NET SDRAM_ADDR(12) LOC="P34" | IOSTANDARD=LVTTL; # SDRAM_ADDR12 is tied to GND on Papilio Pro with MT48LC4M16A2 chip
NET SDRAM_DATA(0) LOC="P9" | IOSTANDARD=LVTTL; # SDRAM_DATA0
NET SDRAM_DATA(1) LOC="P10" | IOSTANDARD=LVTTL; # SDRAM_DATA1
NET SDRAM_DATA(2) LOC="P11" | IOSTANDARD=LVTTL; # SDRAM_DATA2
NET SDRAM_DATA(3) LOC="P12" | IOSTANDARD=LVTTL; # SDRAM_DATA3
NET SDRAM_DATA(4) LOC="P14" | IOSTANDARD=LVTTL; # SDRAM_DATA4
NET SDRAM_DATA(5) LOC="P15" | IOSTANDARD=LVTTL; # SDRAM_DATA5
NET SDRAM_DATA(6) LOC="P16" | IOSTANDARD=LVTTL; # SDRAM_DATA6
NET SDRAM_DATA(7) LOC="P8" | IOSTANDARD=LVTTL; # SDRAM_DATA7
NET SDRAM_DATA(8) LOC="P21" | IOSTANDARD=LVTTL; # SDRAM_DATA8
NET SDRAM_DATA(9) LOC="P22" | IOSTANDARD=LVTTL; # SDRAM_DATA9
NET SDRAM_DATA(10) LOC="P23" | IOSTANDARD=LVTTL; # SDRAM_DATA10
NET SDRAM_DATA(11) LOC="P24" | IOSTANDARD=LVTTL; # SDRAM_DATA11
NET SDRAM_DATA(12) LOC="P26" | IOSTANDARD=LVTTL; # SDRAM_DATA12
NET SDRAM_DATA(13) LOC="P27" | IOSTANDARD=LVTTL; # SDRAM_DATA13
NET SDRAM_DATA(14) LOC="P29" | IOSTANDARD=LVTTL; # SDRAM_DATA14
NET SDRAM_DATA(15) LOC="P30" | IOSTANDARD=LVTTL; # SDRAM_DATA15
NET SDRAM_DQML LOC="P7" | IOSTANDARD=LVTTL; # SDRAM_DQML
NET SDRAM_DQMH LOC="P17" | IOSTANDARD=LVTTL; # SDRAM_DQMH
NET SDRAM_BA(0) LOC="P143" | IOSTANDARD=LVTTL; # SDRAM_BA0
NET SDRAM_BA(1) LOC="P142" | IOSTANDARD=LVTTL; # SDRAM_BA1
NET SDRAM_nWE LOC="P6" | IOSTANDARD=LVTTL; # SDRAM_nWE
NET SDRAM_nCAS LOC="P5" | IOSTANDARD=LVTTL; # SDRAM_nCAS
NET SDRAM_nRAS LOC="P2" | IOSTANDARD=LVTTL; # SDRAM_nRAS
NET SDRAM_CS LOC="P1" | IOSTANDARD=LVTTL; # SDRAM_CS
NET SDRAM_CLK LOC="P32" | IOSTANDARD=LVTTL; # SDRAM_CLK
NET SDRAM_CKE LOC="P33" | IOSTANDARD=LVTTL; # SDRAM_CKE
# End User LED
#NET LED1 LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; # LED1
# JTAG pins
#NET JTAG_TMS LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS
#NET JTAG_TCK LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK
#NET JTAG_TDI LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI
#NET JTAG_TDO LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO
# Flash memory pins
NET FLASH_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS
NET FLASH_CK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK
NET FLASH_SI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI
NET FLASH_SO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO