plus4_2.wcfg

<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
   <wave_state>
   </wave_state>
   <db_ref_list>
      <db_ref path="C:/Users/ISHE/Documents/Cloud/FPGAdev/Plus4/Plus4_testbench2_isim_beh.wdb" id="1" type="auto">
         <top_modules>
            <top_module name="Plus4_testbench2" />
            <top_module name="glbl" />
         </top_modules>
      </db_ref>
   </db_ref_list>
   <WVObjectSize size="3" />
   <wvobject fp_name="group31" type="group">
      <obj_property name="label">SDRAM</obj_property>
      <obj_property name="DisplayName">label</obj_property>
   </wvobject>
   <wvobject fp_name="/Plus4_testbench2/CLK32" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">CLK32</obj_property>
      <obj_property name="ObjectShortName">CLK32</obj_property>
   </wvobject>
   <wvobject fp_name="/Plus4_testbench2/CLK28" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">CLK28</obj_property>
      <obj_property name="ObjectShortName">CLK28</obj_property>
   </wvobject>
</wave_config>