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esp32_sha.c
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esp32_sha.c
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/* esp32_sha.c
*
* Copyright (C) 2006-2023 wolfSSL Inc.
*
* This file is part of wolfSSL.
*
* wolfSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
/*
* ESP32-C3: https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf
* see page 335: no SHA-512
*
*/
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
/* Reminder: user_settings.h is needed and included from settings.h
* Be sure to define WOLFSSL_USER_SETTINGS, typically in CMakeLists.txt */
#include <wolfssl/wolfcrypt/settings.h>
#if defined(WOLFSSL_ESPIDF) /* Entire file is only for Espressif EDP-IDF */
#include "sdkconfig.h" /* programmatically generated from sdkconfig */
#include <wolfssl/wolfcrypt/port/Espressif/esp32-crypt.h>
/*****************************************************************************/
/* this entire file content is excluded when NO_SHA, NO_SHA256
* or when using WC_SHA384 or WC_SHA512
*/
#if !defined(NO_SHA) || !defined(NO_SHA256) || defined(WC_SHA384) || \
defined(WC_SHA512)
#include "wolfssl/wolfcrypt/logging.h"
/* this entire file content is excluded if not using HW hash acceleration */
#if defined(WOLFSSL_ESP32_CRYPT) && \
!defined(NO_WOLFSSL_ESP32_CRYPT_HASH)
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
#include <hal/sha_hal.h>
#include <hal/sha_ll.h>
#include <hal/clk_gate_ll.h>
#else
#include <hal/clk_gate_ll.h> /* ESP32-WROOM */
#endif
#include <wolfssl/wolfcrypt/sha.h>
#include <wolfssl/wolfcrypt/sha256.h>
#include <wolfssl/wolfcrypt/sha512.h>
#include "wolfssl/wolfcrypt/port/Espressif/esp32-crypt.h"
#include "wolfssl/wolfcrypt/error-crypt.h"
#ifdef NO_INLINE
#include <wolfssl/wolfcrypt/misc.h>
#else
#define WOLFSSL_MISC_INCLUDED
#include <wolfcrypt/src/misc.c>
#endif
static const char* TAG = "wolf_hw_sha";
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
/* keep track of the currently active SHA hash object for interleaving */
const static word32 ** _active_digest_address = 0;
#endif
#ifdef NO_SHA
#define WC_SHA_DIGEST_SIZE 20
#endif
#if defined(DEBUG_WOLFSSL)
/* Only when debugging, we'll keep tracking of block numbers. */
static int this_block_num = 0;
#endif
/* RTOS mutex or just InUse variable */
#if defined(SINGLE_THREADED)
static int InUse = 0;
#else
static wolfSSL_Mutex sha_mutex = NULL;
#endif
#ifdef WOLFSSL_DEBUG_MUTEX
#ifndef WOLFSSL_TEST_STRAY
/* unless turned on, we won't be testing for strays */
#define WOLFSSL_TEST_STRAY 0
#endif
#endif
/* usage metrics can be turned on independently of debugging */
#ifdef WOLFSSL_HW_METRICS
static unsigned long esp_sha_hw_copy_ct = 0;
static unsigned long esp_sha1_hw_usage_ct = 0;
static unsigned long esp_sha1_sw_fallback_usage_ct = 0;
static unsigned long esp_sha_reverse_words_ct = 0;
static unsigned long esp_sha1_hw_hash_usage_ct = 0;
static unsigned long esp_sha2_224_hw_hash_usage_ct = 0;
static unsigned long esp_sha2_256_hw_hash_usage_ct = 0;
static unsigned long esp_sha256_sw_fallback_usage_ct = 0;
static unsigned long esp_byte_reversal_checks_ct = 0;
static unsigned long esp_byte_reversal_needed_ct = 0;
#endif
#if defined(ESP_MONITOR_HW_TASK_LOCK)
static void * mutex_ctx_owner = 0;
static TaskHandle_t mutex_ctx_task = 0;
#ifdef WOLFSSL_DEBUG_MUTEX
static portMUX_TYPE sha_crit_sect = portMUX_INITIALIZER_UNLOCKED;
WC_ESP32SHA* stray_ctx;
/* each ctx keeps track of the intializer for HW. when debugging
* we'll have a global variable to indicate which has the lock. */
static int _sha_lock_count = 0;
static int _sha_call_count = 0;
int esp_sha_call_count(void)
{
return _sha_call_count;
}
int esp_sha_lock_count(void)
{
return _sha_lock_count;
}
void* esp_sha_mutex_ctx_owner(void)
{
void* ret = 0;
taskENTER_CRITICAL(&sha_crit_sect);
{
ret = mutex_ctx_owner;
}
taskEXIT_CRITICAL(&sha_crit_sect);
return ret;
};
#else
int esp_sha_mutex_ctx_owner(void)
{
return (int)sha_mutex;
}
#endif
#endif
/*
** The wolfCrypt functions for LITTLE_ENDIAN_ORDER typically
** reverse the byte order. Except when the hardware doesn't expect it.
**
** Returns 0 (FALSE) or 1 (TRUE); see wolfSSL types.h
*/
int esp_sha_need_byte_reversal(WC_ESP32SHA* ctx)
{
int ret = TRUE; /* assume we'll need reversal, look for exceptions */
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
if (ctx == NULL) {
ESP_LOGE(TAG, " ctx is null");
/* return true for bad params */
}
else {
#ifdef WOLFSSL_HW_METRICS
{
esp_byte_reversal_checks_ct++;
}
#endif
if (ctx->mode == ESP32_SHA_HW) {
ESP_LOGV(TAG, " No reversal, ESP32_SHA_HW");
ret = FALSE;
}
else {
ret = TRUE;
ESP_LOGV(TAG, " Need byte reversal, %d", ctx->mode);
/* return true for SW; only HW C3 skips reversal at this time. */
#ifdef WOLFSSL_HW_METRICS
{
esp_byte_reversal_needed_ct++;
}
#endif
if (ctx->mode == ESP32_SHA_INIT) {
ESP_LOGW(TAG, "esp_sha_need_byte_reversal during init?");
ESP_LOGW(TAG, "forgot to try HW lock first?");
}
}
}
#else
/* other platforms always return true */
#endif
return ret;
}
/* esp_sha_init
**
** ctx: any wolfSSL ctx from any hash algo
** hash_type: the specific wolfSSL enum for hash type
**
** Initializes ctx based on chipset capabilities and current state.
** Active HW states, such as from during a copy operation, are demoted to SW.
** For hash_type not available in HW, set SW mode.
**
** See esp_sha_init_ctx(ctx)
*/
int esp_sha_init(WC_ESP32SHA* ctx, enum wc_HashType hash_type)
{
int ret = 0;
#if defined(CONFIG_IDF_TARGET_ESP32) || \
defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
switch (hash_type) { /* check each wolfSSL hash type WC_[n] */
case WC_HASH_TYPE_SHA:
ctx->sha_type = SHA1; /* assign Espressif SHA HW type */
ret = esp_sha_init_ctx(ctx);
break;
case WC_HASH_TYPE_SHA224:
#if defined(CONFIG_IDF_TARGET_ESP32S2) || \
defined(CONFIG_IDF_TARGET_ESP32S3)
ctx->sha_type = SHA2_224; /* assign Espressif SHA HW type */
ret = esp_sha_init_ctx(ctx);
#else
/* Don't call init, always SW as there's no HW. */
ctx->mode = ESP32_SHA_SW;
#endif
break;
case WC_HASH_TYPE_SHA256:
ctx->sha_type = SHA2_256; /* assign Espressif SHA HW type */
ret = esp_sha_init_ctx(ctx);
break;
#if defined(CONFIG_IDF_TARGET_ESP32S2) || \
defined(CONFIG_IDF_TARGET_ESP32S3)
case WC_HASH_TYPE_SHA384:
ctx->mode = ESP32_SHA_SW;
ctx->sha_type = SHA2_384; /* Espressif type, but we won't use HW */
break;
#else
case WC_HASH_TYPE_SHA384:
ctx->sha_type = SHA2_384; /* assign Espressif SHA HW type */
ret = esp_sha_init_ctx(ctx);
break;
#endif
case WC_HASH_TYPE_SHA512:
ctx->sha_type = SHA2_512; /* assign Espressif SHA HW type */
ret = esp_sha_init_ctx(ctx);
break;
#ifndef WOLFSSL_NOSHA512_224
case WC_HASH_TYPE_SHA512_224:
/* Don't call init, always SW as there's no HW. */
ctx->mode = ESP32_SHA_SW;
ctx->sha_type = SHA2_512; /* Espressif type, but we won't use HW */
break;
#endif
#ifndef WOLFSSL_NOSHA512_256
case WC_HASH_TYPE_SHA512_256:
/* Don't call init, always SW as there's no HW. */
ctx->mode = ESP32_SHA_SW;
ctx->sha_type = SHA2_512; /* Espressif type, but we won't use HW */
break;
#endif
default:
ret = esp_sha_init_ctx(ctx);
ESP_LOGW(TAG, "Unexpected hash_type in esp_sha_init");
break;
}
#elif defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
switch (hash_type) { /* check each wolfSSL hash type WC_[n] */
#ifndef NO_SHA
case WC_HASH_TYPE_SHA:
ctx->sha_type = SHA1; /* assign Espressif SHA HW type */
ret = esp_sha_init_ctx(ctx);
break;
#endif
case WC_HASH_TYPE_SHA224:
ctx->sha_type = SHA2_224; /* assign Espressif SHA HW type */
ret = esp_sha_init_ctx(ctx);
break;
case WC_HASH_TYPE_SHA256:
ctx->sha_type = SHA2_256; /* assign Espressif SHA HW type */
ret = esp_sha_init_ctx(ctx);
break;
default:
/* We fall through to SW when there's no enabled HW, above. */
ctx->mode = ESP32_SHA_SW;
ret = 0;
/* If there's no HW, the ctx reference should cause build error.
** The type should be gated away when there's no HW at all! */
ctx->isfirstblock = true;
ctx->sha_type = hash_type;
ESP_LOGW(TAG, "Unsupported hash_type = %d in esp_sha_init, "
"falling back to SW", hash_type);
break;
}
#else
/* other chipsets will be implemented here */
ESP_LOGW(TAG, "SW Fallback; CONFIG_IDF_TARGET = %s", CONFIG_IDF_TARGET);
ctx->mode = ESP32_SHA_SW;
#endif /* CONFIG_IDF_TARGET_ESP32 ||
* CONFIG_IDF_TARGET_ESP32S2 ||
* CONFIG_IDF_TARGET_ESP32S3 */
return ret;
}
#ifndef NO_SHAx /* TODO cannot currently turn off SHA */
/* we'll call a separate init as there's only 1 HW acceleration */
int esp_sha_init_ctx(WC_ESP32SHA* ctx)
{
if (ctx->initializer == NULL) {
ESP_LOGV(TAG, "regular init of blank WC_ESP32SHA ctx");
/* we'll keep track of who initialized this */
ctx->initializer = ctx; /* save our address in the initializer */
#ifdef ESP_MONITOR_HW_TASK_LOCK
{
/* Keep track of which freeRTOS task actually locks HW */
ctx->task_owner = xTaskGetCurrentTaskHandle();
}
#endif
ctx->mode = ESP32_SHA_INIT;
}
else {
/* things may be more interesting when previously initialized */
if (ctx->initializer == ctx) {
/* We're likely re-using an existing object previously initialized.
** There's of course a non-zero probability that garbage data is
** the same pointer value, but that's highly unlikely; We'd need
** to discard, then re-init to same memory location for a matching
** initializer. */
ESP_LOGV(TAG, "re-using existing WC_ESP32SHA ctx");
/* we should never have an unexpected mode in a known ctx */
switch (ctx->mode) {
case ESP32_SHA_FREED:
ESP_LOGW(TAG, "Warning: ESP32_SHA_FREED status");
#ifdef ESP_MONITOR_HW_TASK_LOCK
if (ctx->task_owner == xTaskGetCurrentTaskHandle()) {
esp_sha_hw_unlock(ctx);
}
else {
ESP_LOGW(TAG, "Warning: unable to unlock ctx mutex ");
}
#else
esp_sha_hw_unlock(ctx);
#endif
ctx->mode = ESP32_SHA_INIT;
/* fall through to init */
case ESP32_SHA_INIT:
case ESP32_SHA_SW:
/* nothing interesting here */
break;
case ESP32_SHA_HW:
/* This will be dealt with below: likely demote to SW */
break;
case ESP32_SHA_HW_COPY:
/* This is an interesting mode, caller gave HW mode hint */
ESP_LOGI(TAG, "ALERT: ESP32_SHA_HW_COPY?");
break;
default:
/* This should almost never occur. We'd need to have an
** uninitialized ctx that just happens to include the
** breadcrumb initializer with the same address. */
ESP_LOGW(TAG, "ALERT: unexpected WC_ESP32SHA ctx mode: "
"%d. ", ctx->mode);
ctx->mode = ESP32_SHA_INIT;
break;
}
/* We don't need to do anything here,
** this section for diagnostics only.
** May need to unlock HW, below. */
} /* ctx->initializer == ctx */
else {
/* We may end up here with either dirty memory
** or copied SHA ctx.
**
** Any copy function should have already set mode = ESP32_SHA_INIT.
**
** In either case, initialize: */
ctx->initializer = ctx; /* set a new address */
#ifdef ESP_MONITOR_HW_TASK_LOCK
{
/* not HW mode, so we are not interested in task owner */
ctx->task_owner = 0;
}
#endif
/* Always set to ESP32_SHA_INIT, but give debug info as to why: */
switch (ctx->mode) {
case ESP32_SHA_FREED:
ESP_LOGE(TAG, "ERROR: unexpected ESP32_SHA_FREED");
ctx->mode = ESP32_SHA_INIT;
break;
case ESP32_SHA_INIT:
/* if we are already in init mode, nothing to do. */
break;
case ESP32_SHA_SW:
/* this should rarely, if ever occur */
ESP_LOGW(TAG, "ALERT: unexpected SW WC_ESP32SHA ctx mode. "
"Copied? Revert to ESP32_SHA_INIT.");
ctx->mode = ESP32_SHA_INIT;
break;
case ESP32_SHA_HW:
/* this should rarely, if ever occur. */
ESP_LOGW(TAG, "ALERT: unexpected HW WC_ESP32SHA ctx mode. "
"Copied?");
ctx->mode = ESP32_SHA_INIT;
break;
case ESP32_SHA_HW_COPY:
/* This is an interesting but acceptable situation:
** an anticipated active HW copy that will demote to SW. */
ESP_LOGV(TAG, "HW WC_ESP32SHA ctx mode = "
"ESP32_SHA_HW_COPY.");
break;
default:
/* this will frequently occur during new init */
ESP_LOGV(TAG, "ALERT: unexpected WC_ESP32SHA ctx mode. "
"Uninitialized?");
ctx->mode = ESP32_SHA_INIT;
break;
} /* switch */
} /* ctx->initializer != ctx */
} /* ctx->initializer != NULL */
/*
** After possibly changing the mode (above) handle current mode:
*/
switch (ctx->mode) {
case ESP32_SHA_INIT:
/* Likely a fresh, new SHA, as desired. */
ESP_LOGV(TAG, "Normal ESP32_SHA_INIT");
break;
case ESP32_SHA_HW:
/* We're already in hardware mode, so release. */
/* Interesting, but normal. */
ESP_LOGV(TAG, ">> HW unlock.");
/* During init is the ONLY TIME we call unlock.
** If there's a problem, likely some undesired operation
** outside of wolfSSL.
*/
/* TODO debug check if HW actually locked; */
esp_sha_hw_unlock(ctx);
ctx->mode = ESP32_SHA_INIT;
break;
case ESP32_SHA_HW_COPY:
/* When we init during a known active HW copy, revert to SW. */
ESP_LOGV(TAG, "Planned revert to SW during copy.");
ctx->mode = ESP32_SHA_SW;
break;
case ESP32_SHA_SW:
/* This is an interesting situation: likely a call when
** another SHA in progress, but copied. */
ESP_LOGV(TAG, ">> SW Set to init.");
ctx->mode = ESP32_SHA_INIT;
break;
case ESP32_SHA_FAIL_NEED_UNROLL:
/* Oh, how did we get here? likely uninitialized SHA memory.
** User code logic may need attention. */
ESP_LOGW(TAG, "ALERT: \nESP32_SHA_FAIL_NEED_UNROLL\n");
ctx->mode = ESP32_SHA_INIT;
break;
default:
/* Most likely corrupted memory. */
ESP_LOGW(TAG, "ALERT: \nunexpected mode value: "
"%d \n", ctx->mode);
ctx->mode = ESP32_SHA_INIT;
break;
} /* switch (ctx->mode) */
/* reminder: always start isfirstblock = 1 (true) when using HW engine */
/* we're always on the first block at init time (not zero-based!) */
ctx->isfirstblock = true;
ctx->lockDepth = 0; /* new objects will always start with lock depth = 0 */
return ESP_OK; /* Always return success.
* We assume all issues handled, above. */
} /* esp_sha_init_ctx */
/*
** internal SHA ctx copy for ESP HW
*/
int esp_sha_ctx_copy(struct wc_Sha* src, struct wc_Sha* dst)
{
int ret;
if (src->ctx.mode == ESP32_SHA_HW) {
/* this is an interesting situation to copy HW digest to SW */
ESP_LOGV(TAG, "esp_sha_ctx_copy esp_sha_digest_process");
#ifdef WOLFSSL_HW_METRICS
{
esp_sha_hw_copy_ct++;
}
#endif
/* Get a copy of the HW digest, but don't process it. */
ret = esp_sha_digest_process(dst, 0);
if (ret == 0) {
/* Note we arrived here only because
* the src is already in HW mode.
* provide init hint to SW revert: */
dst->ctx.mode = ESP32_SHA_HW_COPY;
/* initializer will be set during init */
ret = esp_sha_init(&(dst->ctx), WC_HASH_TYPE_SHA);
if (ret != 0) {
ESP_LOGE(TAG, "Error during esp_sha_ctx_copy "
"in esp_sha_init.");
}
}
else {
ESP_LOGE(TAG, "Error during esp_sha_ctx_copy "
"in esp_sha_digest_process.");
}
if (dst->ctx.mode == ESP32_SHA_SW) {
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
/* Reverse digest for C2/C3/C6 RISC-V platform
* only when HW enabled but fallback to SW. */
ByteReverseWords(dst->digest, dst->digest, WC_SHA_DIGEST_SIZE);
#ifdef WOLFSSL_HW_METRICS
esp_sha_reverse_words_ct++;
#endif
#endif
/* The normal revert to SW in copy is expected */
ESP_LOGV(TAG, "Confirmed SHA Copy set to SW");
}
else {
/* However NOT reverting to SW is not right.
** This should never happen. */
ESP_LOGW(TAG, "SHA Copy NOT set to SW");
}
} /* (src->ctx.mode == ESP32_SHA_HW */
else { /* src not in HW mode, ok to copy. */
/*
** reminder XMEMCOPY, above: dst->ctx = src->ctx;
** No special HW init needed in SW mode.
** but we need to set our initializer breadcrumb: */
dst->ctx.initializer = &(dst->ctx); /* assign new breadcrumb to dst */
#ifdef ESP_MONITOR_HW_TASK_LOCK
{
/* not HW mode for copy, so we are not interested in task owner */
dst->ctx.task_owner = 0;
}
#endif
ret = 0;
}
return ret;
} /* esp_sha_ctx_copy */
#endif
/*
** internal sha224 ctx copy (no ESP HW)
*/
#ifndef NO_WOLFSSL_ESP32_CRYPT_HASH_SHA224
int esp_sha224_ctx_copy(struct wc_Sha256* src, struct wc_Sha256* dst)
{
/* There's no 224 hardware on ESP32 */
dst->ctx.initializer = &dst->ctx; /* assign the initializer to dst */
#ifdef ESP_MONITOR_HW_TASK_LOCK
{
/* not HW mode for copy, so we are not interested in task owner */
dst->ctx.task_owner = 0;
}
#endif
dst->ctx.mode = ESP32_SHA_SW;
return ESP_OK;
} /* esp_sha224_ctx_copy */
#endif
#ifndef NO_WOLFSSL_ESP32_CRYPT_HASH_SHA256
/*
** internal sha256 ctx copy for ESP HW
*/
int esp_sha256_ctx_copy(struct wc_Sha256* src, struct wc_Sha256* dst)
{
int ret;
if (src->ctx.mode == ESP32_SHA_HW) {
/* Get a copy of the HW digest, but don't process it. */
#ifdef WOLFSSL_DEBUG_MUTEX
{
ESP_LOGI(TAG, "esp_sha256_ctx_copy esp_sha512_digest_process");
}
#endif
ret = esp_sha256_digest_process(dst, 0); /* TODO Use FALSE*/
if (ret == 0) {
/* provide init hint to possibly SW revert */
dst->ctx.mode = ESP32_SHA_HW_COPY;
/* initializer breadcrumb will be set during init */
ret = esp_sha_init(&(dst->ctx), WC_HASH_TYPE_SHA256 );
}
if (dst->ctx.mode == ESP32_SHA_SW) {
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
{
/* Reverse digest byte order for C3 fallback to SW. */
ByteReverseWords(dst->digest,
dst->digest,
WC_SHA256_DIGEST_SIZE);
}
#endif
ESP_LOGV(TAG, "Confirmed wc_Sha256 Copy set to SW");
}
else {
ESP_LOGW(TAG, "wc_Sha256 Copy NOT set to SW");
}
} /* (src->ctx.mode == ESP32_SHA_HW) */
else {
ret = 0;
/*
** reminder this happened in XMEMCOPY: dst->ctx = src->ctx;
** No special HW init needed in SW mode.
** but we need to set our initializer: */
dst->ctx.initializer = &dst->ctx; /* assign the initializer to dst */
#ifdef ESP_MONITOR_HW_TASK_LOCK
{
/* not HW mode, so we are not interested in task owner */
dst->ctx.task_owner = 0;
}
#endif
} /* not (src->ctx.mode == ESP32_SHA_HW) */
return ret;
} /* esp_sha256_ctx_copy */
#endif
#if !(defined(NO_WOLFSSL_ESP32_CRYPT_HASH_SHA384) && \
defined(NO_WOLFSSL_ESP32_CRYPT_HASH_SHA512) \
) && \
(defined(WOLFSSL_SHA384) || defined(WOLFSSL_SHA512))
/*
** internal sha384 ctx copy for ESP HW
*/
int esp_sha384_ctx_copy(struct wc_Sha512* src, struct wc_Sha512* dst)
{
int ret = 0;
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
{
/* We should ever be calling the HW sHA384 copy for this target. */
ESP_LOGW(TAG, "Warning: esp_sha384_ctx_copy() called for %s!",
CONFIG_IDF_TARGET);
ESP_LOGW(TAG, "There's no SHA384 HW for this CONFIG_IDF_TARGET");
}
#else
if (src->ctx.mode == ESP32_SHA_HW) {
/* Get a copy of the HW digest, but don't process it. */
ESP_LOGI(TAG, "esp_sha384_ctx_copy esp_sha512_digest_process");
ret = esp_sha512_digest_process(dst, 0);
if (ret == 0) {
/* provide init hint to SW revert */
dst->ctx.mode = ESP32_SHA_HW_COPY;
/* initializer will be set during init */
ret = esp_sha_init(&(dst->ctx), WC_HASH_TYPE_SHA384);
if (ret != 0) {
ESP_LOGE(TAG, "Error during esp_sha384_ctx_copy "
"in esp_sha_init.");
}
}
else {
ESP_LOGE(TAG, "Error during esp_sha384_ctx_copy "
"in esp_sha512_digest_process.");
}
/* just some diagnostic runtime info */
if (dst->ctx.mode == ESP32_SHA_SW) {
ESP_LOGV(TAG, "Confirmed wc_Sha512 Copy set to SW");
}
else {
ESP_LOGW(TAG, "wc_Sha512 Copy NOT set to SW");
}
} /* src->ctx.mode == ESP32_SHA_HW */
else {
ret = 0;
/*
** reminder this happened in XMEMCOPY, above: dst->ctx = src->ctx;
** No special HW init needed in SW mode.
** but we need to set our initializer: */
dst->ctx.initializer = &dst->ctx; /* assign the initializer to dst */
#ifdef ESP_MONITOR_HW_TASK_LOCK
{
/* not HW mode for copy, so we are not interested in task owner */
dst->ctx.task_owner = 0;
}
#endif
} /* not (src->ctx.mode == ESP32_SHA_HW) */
#endif
return ret;
} /* esp_sha384_ctx_copy */
#endif
#if !(defined(NO_WOLFSSL_ESP32_CRYPT_HASH_SHA384) && \
defined(NO_WOLFSSL_ESP32_CRYPT_HASH_SHA512) \
) && \
(defined(WOLFSSL_SHA384) || defined(WOLFSSL_SHA512))
/*
** Internal sha512 ctx copy for ESP HW.
** If HW already active, fall back to SW for this ctx.
*/
int esp_sha512_ctx_copy(struct wc_Sha512* src, struct wc_Sha512* dst)
{
int ret = ESP_OK; /* Assume success (zero) */
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
/* there's no SHA512 HW on the RISC-V SoC so there's nothing to do. */
#elif defined(CONFIG_IDF_TARGET_ESP32) || \
defined(CONFIG_IDF_TARGET_ESP32S2) || \
defined(CONFIG_IDF_TARGET_ESP32S3)
if (src->ctx.mode == ESP32_SHA_HW) {
/* Get a copy of the HW digest, but don't process it. */
ESP_LOGI(TAG, "esp_sha512_ctx_copy esp_sha512_digest_process");
ret = esp_sha512_digest_process(dst, 0);
if (ret == 0) {
/* provide init hint to SW revert */
dst->ctx.mode = ESP32_SHA_HW_COPY;
/* initializer will be set during init
** reminder we should never arrive here for
** ESP32 SHA512/224 or SHA512/224, as there's no HW */
ret = esp_sha_init(&(dst->ctx), WC_HASH_TYPE_SHA512);
}
if (dst->ctx.mode == ESP32_SHA_SW) {
ESP_LOGV(TAG, "Confirmed wc_Sha512 Copy set to SW");
}
else {
ESP_LOGW(TAG, "wc_Sha512 Copy NOT set to SW");
}
} /* src->ctx.mode == ESP32_SHA_HW */
else {
ret = 0;
/* reminder this happened in XMEMCOPY, above: dst->ctx = src->ctx;
** No special HW init needed when not in active HW mode.
** but we need to set our initializer breadcrumb: */
/* TODO: instead of what is NOT supported, gate on what IS known to be supported */
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && \
!defined(CONFIG_IDF_TARGET_ESP32C3) && \
!defined(CONFIG_IDF_TARGET_ESP32C6)
dst->ctx.initializer = &dst->ctx; /*breadcrumb is this ctx address */
#endif
#ifdef ESP_MONITOR_HW_TASK_LOCK
{
/* not HW mode for copy, so we are not interested in task owner */
dst->ctx.task_owner = 0;
}
#endif
}
#endif
return ret;
} /* esp_sha512_ctx_copy */
#endif
/*
** Determine the digest size, depending on SHA type.
**
** See FIPS PUB 180-4, Instruction Section 1.
**
** See ESP32 shah.h for values:
**
** enum SHA_TYPE {
** SHA1 = 0,
** SHA2_256,
** SHA2_384,
** SHA2_512,
** SHA_INVALID = -1,
** };
**
** given the SHA_TYPE (see Espressif sha.h) return WC digest size.
**
** Returns zero for bad digest size type request.
**
*/
static word32 wc_esp_sha_digest_size(WC_ESP_SHA_TYPE type)
{
int ret = 0;
ESP_LOGV(TAG, " esp_sha_digest_size");
#if CONFIG_IDF_TARGET_ARCH_RISCV
/*
* SHA1 = 0,
* SHA2_224,
* SHA2_256,
*/
switch (type) {
#ifndef NO_SHA
case SHA1: /* typically 20 bytes */
ret = WC_SHA_DIGEST_SIZE;
break;
#endif
#ifdef WOLFSSL_SHA224
case SHA2_224:
ret = WC_SHA224_DIGEST_SIZE;
break;
#endif
#ifndef NO_SHA256
case SHA2_256: /* typically 32 bytes */
ret = WC_SHA256_DIGEST_SIZE;
break;
#endif
default:
ESP_LOGE(TAG, "Bad SHA type in wc_esp_sha_digest_size");
ret = 0;
break;
}
#else
/* Xtensa */
switch (type) {
#ifndef NO_SHA
case SHA1: /* typically 20 bytes */
ret = WC_SHA_DIGEST_SIZE;
break;
#endif
#ifdef WOLFSSL_SHA224
#if defined(CONFIG_IDF_TARGET_ESP32S2) || \
defined(CONFIG_IDF_TARGET_ESP32S3)
case SHA2_224:
ret = WC_SHA224_DIGEST_SIZE;
break;
#endif
#endif
#ifndef NO_SHA256
case SHA2_256: /* typically 32 bytes */
ret = WC_SHA256_DIGEST_SIZE;
break;
#endif
#ifdef WOLFSSL_SHA384
case SHA2_384:
ret = WC_SHA384_DIGEST_SIZE;
break;
#endif
#ifdef WOLFSSL_SHA512
case SHA2_512: /* typically 64 bytes */
ret = WC_SHA512_DIGEST_SIZE;
break;
#endif
default:
ESP_LOGE(TAG, "Bad SHA type in wc_esp_sha_digest_size");
ret = 0;
break;
}
#endif
return ret; /* Return value is a size, not an error code. */
} /* wc_esp_sha_digest_size */
/*
** wait until all engines becomes idle
*/
static int wc_esp_wait_until_idle(void)
{
int ret = 0; /* assume success */
int loop_ct = 10000;
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
/* ESP32-C3 and ESP32-C6 RISC-V */
while ((sha_ll_busy() == true) && (loop_ct > 0)) {
loop_ct--;
/* do nothing while waiting. */
}
#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
while (REG_READ(SHA_BUSY_REG)) {
/* do nothing while waiting. */
}
#else
while ((DPORT_REG_READ(SHA_1_BUSY_REG) != 0) ||
(DPORT_REG_READ(SHA_256_BUSY_REG) != 0) ||
(DPORT_REG_READ(SHA_384_BUSY_REG) != 0) ||
(DPORT_REG_READ(SHA_512_BUSY_REG) != 0)) {
/* do nothing while waiting. */
}
#endif
if (loop_ct <= 0)
{
ESP_LOGI(TAG, "too long to exit wc_esp_wait_until_idle");
}
return ret;
} /* wc_esp_wait_until_idle */
/*
** hack alert. there really should have been something implemented
** in Espressif periph_ctrl.c to detect ref_counts[periph] depth.
**
** since there is not at this time, we have this brute-force method.
**
** when trying to unwrap an arbitrary depth of peripheral-enable(s),
** we'll check the register upon *enable* to see if we actually did.
**
** Note that enable / disable only occurs when ref_counts[periph] == 0
**
*/
int esp_unroll_sha_module_enable(WC_ESP32SHA* ctx)
{
/* if we end up here, there was a prior unexpected fail and
* we need to unroll enables */
int ret = 0; /* assume success unless proven otherwise */
int actual_unroll_count = 0;
int max_unroll_count = 1000; /* never get stuck in a hardware wait loop */
#if defined(CONFIG_IDF_TARGET_ESP32)
word32 this_sha_mask; /* this is the bit-mask for our SHA CLK_EN_REG */
#endif
if (ctx == NULL) {
ESP_LOGE(TAG, "esp_unroll_sha_module_enable called with null ctx.");
return BAD_FUNC_ARG;
}
#if defined(CONFIG_IDF_TARGET_ESP32C2) || \
defined(CONFIG_IDF_TARGET_ESP8684) || \
defined(CONFIG_IDF_TARGET_ESP32C3) || \
defined(CONFIG_IDF_TARGET_ESP32C6)
/************* RISC-V Architecture *************/
(void)max_unroll_count;
(void)_active_digest_address;
ets_sha_disable();
/* We don't check for unroll as done below, for Xtensa*/
#else
/************* Xtensa Architecture *************/
/* unwind prior calls to THIS ctx. decrement ref_counts[periph]
** only when ref_counts[periph] == 0 does something actually happen. */
/* once the value we read is a 0 in the DPORT_PERI_CLK_EN_REG bit
* then we have fully unrolled the enables via ref_counts[periph]==0 */
#if defined(CONFIG_IDF_TARGET_ESP32S2) ||defined(CONFIG_IDF_TARGET_ESP32S3)
/* once the value we read is a 0 in the DPORT_PERI_CLK_EN_REG bit
* then we have fully unrolled the enables via ref_counts[periph]==0 */
while (periph_ll_periph_enabled(PERIPH_SHA_MODULE)) {
#else
/* this is the bit-mask for our SHA CLK_EN_REG */
this_sha_mask = periph_ll_get_clk_en_mask(PERIPH_SHA_MODULE);
asm volatile("memw");